removed unneeded exit
Merge pull request #273 from dpefour/master

Major updates to insert_buffer.tcl
- write native compile script for ModelSim
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140626103024. Submit user: rajklair, branch: master.
cr:943632 - fixed verilog_define propagation issue
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140626160929. Submit user: rajklair, branch: master.
805342 - do not sort compile order for verilog and vhdl (default behavior)
Merge branch 'master' of http://github.com/rajklair/XilinxTclStore into rajklair-master
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140626171055. Submit user: rajklair, branch: master.
fixed msg format (send_msg_id)
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140627082438. Submit user: rajklair, branch: master.
added diff examples
merging upstream changes
updated tclIndex
Merged pull request 278 for diff