CHROMIUM: ARM: dts: big: run trackpad I2C at 400Khz on Rev3+

Big rev3 and later boards are expected to have the rework necessary
to run the trackpad I2C bus at 400Khz reliably.

BUG=chrome-os-partner:28903
TEST=Trackpad works at 400Khz on reworked rev2 board.

Change-Id: I7d14fc626c7d3d7f5b705a4d8ffb331ee995d4be
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200290
Reviewed-by: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit 96170f09267b4b77b4106ace10cc8904de15d034)
Reviewed-on: https://chromium-review.googlesource.com/201482
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org>
Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: video: tegra: Active dc/sor register change immediately

When doing DP attach, we need to make sure the register change to take
effect immediately, otherwise it may fail to catch the attach timing.

BUG=chrome-os-partner:28128
TEST=Display works and system boots up

Change-Id: Ie9ee0e40aaa9aada0ce769f132c0e2aa23fcd4fa
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/200418
Tested-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201424
Reviewed-by: Thomas Lin <Thomas_Lin@compal.com>
Commit-Queue: Thomas Lin <Thomas_Lin@compal.com>
Tested-by: Thomas Lin <Thomas_Lin@compal.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: powergate: Powergate refcount based partitions when boot

venc/disp1/disp2/sor are 4 powergate partitions which are refcount
based. CoreBoot may enable something(e.g: display) so when kernel
takes over the system, we need to make sure the hardware environment
is clean.

So this change makes powergate driver powergate all these 4 partitions
when booting, so that the refcounts for these 4 partitions can be zero.

BUG=chrome-os-partner:28128
TEST=Display works and system boots up

Signed-off-by: Mark Zhang <markz@nvidia.com>

Change-Id: I93d44e5424f1e6bf11685cbc2cf0b1d33a63c4a0
Reviewed-on: https://chromium-review.googlesource.com/200419
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201419
Reviewed-by: Thomas Lin <Thomas_Lin@compal.com>
Commit-Queue: Thomas Lin <Thomas_Lin@compal.com>
Tested-by: Thomas Lin <Thomas_Lin@compal.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: clk: tegra: fix VCO rate

Fix VCO rate by taking vco_min into account.

BUG=chrome-os-partner:28128
TEST=check if the calculated VCO rate is bigger than the VCO_MIN, it
     should be.

Change-Id: I74ebda42f0c252002194d487d3d8c033ce34f9b0
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/200527
Tested-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-by: <pdeschrijver@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201441
Reviewed-by: Thomas Lin <Thomas_Lin@compal.com>
Commit-Queue: Thomas Lin <Thomas_Lin@compal.com>
Tested-by: Thomas Lin <Thomas_Lin@compal.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: clk: tegra124: add flag TEGRA_PLL_ACCURATE for pll_dp

We need clock rate of "PLL_DP" to be accurate, add flags
TEGRA_PLL_ACCURATE for clock "PLL_DP".

BUG=chrome-os-partner:28128
TEST=Read clock rate of pll_dp in clk_summary, it should be 270MHz
     instead of 268MHz.

Change-Id: I4208b849558daa48c0bf370f561ec64cfb6a57fc
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/200542
Tested-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-by: <pdeschrijver@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201361
Reviewed-by: Thomas Lin <Thomas_Lin@compal.com>
Commit-Queue: Thomas Lin <Thomas_Lin@compal.com>
Tested-by: Thomas Lin <Thomas_Lin@compal.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: dt: Increase big panel power-off time

The Full HD panel of BIG requires 500ms power-off time.
Since we can't define different skus in DT, we have to
increase the power-off time in BIG DT to make all panels
happy.

BUG=chrome-os-partner:28128
TEST=Display works and system boots up normally

Change-Id: I19794ff7b462d8dbae81c9e224e8caaca0ed2a8d
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/200545
Tested-by: Bill Huang <bilhuang@nvidia.com>
Tested-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201450
Reviewed-by: Thomas Lin <Thomas_Lin@compal.com>
Commit-Queue: Thomas Lin <Thomas_Lin@compal.com>
Tested-by: Thomas Lin <Thomas_Lin@compal.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: ARM: dts: blaze: clock GEN2 I2C at 400KHz

Blaze shall be able to clock trackpad/touchpad I2C bus at 400KHz.
Change the dt setting accordingly to improve the performance.

BUG=chrome-os-partner:29023
TEST=emerged blaze kernel, captured the waveform from gen2 i2c bus,
scl running at ~400Kz and the waveform looks good.

Change-Id: I381627cca42e66406a90518a4fdac3e440f0c928
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/200720
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 62fd106fe44e05d75867ce92a2d4706f87ebfb3c)
Reviewed-on: https://chromium-review.googlesource.com/202217
CHROMIUM: ARM: dt: blaze: change AS3722 adc channel

Blaze uses ADC channel 21 to sense AS3728 SD6 regulator
temperature. Change the dt setting accordingly.

BUG=chrome-os-partner:28994
TEST=cat /sys/class/thermal/thermal_zone5/temp returned a fixed
and invalid value, but the value looks good and changes with this
change.

Change-Id: I3228c8d7e76b8012be097c407e75fc4cace1e182
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/199999
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit e1c7d01ecb32c5f37b822e8ae8b8782dfd76ea47)
Reviewed-on: https://chromium-review.googlesource.com/202235
CHROMIUM: input: elants_i2c driver fixes from 3.8

CHROMIUM: input: elants_i2c driver bug fix

This patch fixes a bug from patch set 11 of CL I9dd69608792767e0794a80833d04b1f34957fc8b.
(CL Link https://chromium-review.googlesource.com/#/c/193588)

This bug arises from moving a if statement into a for loop.

Original:

if (finger_stat == 0)
	break;

After:

for (...; ... && i < num_fingers; ...)

It makes data parsing behavior and finger report uncorrect.
If a finger data is not with finger ID 0, parsing process will not get the correct data.
The scenario is as following:
1. One finger on touchscreen (with finger ID 0) and drawing
2. Add another finger on touchscreen (with finger ID 1), now drawing with two fingers on touchscreen.
3. The first finger (with finger ID 0) leaves touchscreen => parsing behavior is uncorrect and drawing breaks.

BUG=None
TEST=on Elan touchscreen, boot and touchscreen works.

Original-change-Id: Ie1b62bfdfc2901a0acec7958d7436052fa15f8b8
Originally-signed-off-by: Liang Po-Hsiang <iamshyang@gmail.com>
Originally-reviewed-on: https://chromium-review.googlesource.com/201057
Originally-reviewed-by: Charles Mooney <charliemooney@chromium.org>
Originally-tested-by: Charles Mooney <charliemooney@chromium.org>
Originally-Commit-Queue: Charles Mooney <charliemooney@chromium.org>

CHROMIUM: input: elants_i2c version sysfs entries

This CL divides 2-byte test version into test version (1-byte) and solution version (1-byte).

BUG=None
TEST=on Elan touchscreen, boot and touchscreen works.

Original-change-Id: Ic3eff74de5aac64884fb113e40af36410796b3ba
Originally-signed-off-by: Liang Po-Hsiang <iamshyang@gmail.com>
Originally-reviewed-on: https://chromium-review.googlesource.com/201048
Originally-reviewed-by: Charles Mooney <charliemooney@chromium.org>
Originally-tested-by: Charles Mooney <charliemooney@chromium.org>
Originally-Commit-Queue: Charles Mooney <charliemooney@chromium.org>

CHROMIUM: input: elants_i2c driver bug fix (update)

This patch is based on CL Ie1b62bfdfc2901a0acec7958d7436052fa15f8b8.

A new operation is added to reduce unnecessary computation if num_fingers becomes 0 in elan_mt_event().

BUG=None
TEST=on Elan touchscreen, boot and touchscreen works.

Original-change-Id: If9133bdfdba53e6c19ae243a4605915d801130f9
Originally-signed-off-by: Liang Po-Hsiang <iamshyang@gmail.com>
Originally-reviewed-on: https://chromium-review.googlesource.com/201163
Originally-reviewed-by: Charles Mooney <charliemooney@chromium.org>
Originally-commit-Queue: Charles Mooney <charliemooney@chromium.org>
Originally-tested-by: Charles Mooney <charliemooney@chromium.org>

Change-Id: I27f1701fa1d3f0cc2ea388ad255163b8181dc282
Signed-off-by: Charlie Mooney <charliemooney@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202573
CHROMIUM: config: blaze: enable elan touch screen driver in base.config

Add CONFIG_TOUCHSCREEN_ELAN=y in base.config to enable elan touch screen driver.

BUG=chrome-os-partner:27621
TEST=manual
build kernel which enable elan touch screen driver in base.config and update elan touch screen FW.
check if touch screen work or not

Change-Id: I42aecbfae54e4e2897d265016e5167729d2588e9
Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com>
Reviewed-by: Charles Mooney <charliemooney@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200539
Tested-by: Chen Wisley <wisley.chen@quantatw.com>
Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org>
(cherry picked from commit e6cb5d7fa82cd44f0fcae8fe85a77c10347c5ae1)
Reviewed-on: https://chromium-review.googlesource.com/202556
Commit-Queue: Charles Mooney <charliemooney@chromium.org>
Tested-by: Charles Mooney <charliemooney@chromium.org>
CHROMIUM: ARM: dts: blaze: add Hynix/Micro/Samsung 4GB EMC table

Add 4G EMC table for:
Hynix H5TC8G63AFR-PBR, ramcode = 8
Micro MT41K512M16TNA-125:E, ramcode = 9
Samsung K4B8G1646Q, ramcode = 10

BUG=chrome-os-partner:29410
TEST=emerged kernel, booted successfully on the three blaze sku.

Change-Id: Id8e335488e98f01b3c3b1d90ab9a7c95bc0d8fda
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/202557
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 2692b41775865d7ff92c3b3f17067ee5ea92e847)
Reviewed-on: https://chromium-review.googlesource.com/202622
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>