target-mips: fix CP0.BadVAddr by stopping translation on Address error

BadVAddr is supposed to capture the most recent address that caused
the exception. Currently this is not happening as translation is not stopped
and BadVAddr is updated with subsequent addresses.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: apply CP0.PageMask before writing into TLB entry

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: use CP0EnLo_XI instead of magic number

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: add mips32r6-generic CPU

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
disas/mips: fix for some R6 instructions

Fix for some incorrectly disassembled R6 instructions

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: implement Config5.LLB feature

Config5.LLB feature makes LLBit accessible by software through CP0_LLAddr[0].
The existing implementation in QEMU doesn't allow to determine llbit between
LL and SC instruction: LL remembers lladdr + value, and SC succeeds if the value
hasn't changed - otherwise SC will fail.

In order to implement Config5.LLB the following changes have been made:
* added LLBIT hflag which is set by LL/LLD, cleared by SC/SCD (these
  instruction now will terminate translation block) and also can be read and
  cleared when accessing CP0_LLAddr[0] and also:
* when LLBIT is set all stores are compared to LLAddr, if they are referring
  to the same address then LLBIT is cleared (might have impact on performance).

Limitation:
* on multicore LLAddr[0] will not be updated (cleared) if other core triggered
  an event which clears llbit.

Add also ERETNC instruction, which is identical to ERET except that an ERETNC
will not clear the LLbit that is set by execution of an LL instruction, and thus
when placed between an LL and SC sequence, will never cause the SC to fail.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: enable LPA in MIPS64

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: support mthc0 and mfhc0 in MIPS64

When CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0
of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate
for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or
EntryLo1.
Therefore creating separate functions generating for EntryLo0 and EntryLo1.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: add Config5.FRE support

FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available.

Config5.FRE: Allows emulation of Status.FR=0 handling on a 64-bit FPU with
             Status.FR=1. When enabled all single-precision FP arithmetic
             instructions cause a Reserved Instructions exception.

Config5.UFE: Allows user to write Config5.FRE using CTC1, and Config5.FRE
             using CFC1.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Merge pull request #21 from lalrae/i6400-mips64r6-PRIP4

This pull request contains the following features required for I6400 emulation:
* Config5.FRE feature allowing emulation of Status.FR=0 on a 64-bit FPU
  with Status.FR=1.
* Config5.LLB feature which makes LLbit visible to the software through
  CP0.LLAddr[0], it also adds ERETNC instruction.
* Enable 48-bit Physical Address on MIPS64.
* Bug fixes

Updates for #17

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>