media: video: fix clock settings for Tegra VI driver

 - remove reduntant emc clock rate set which is controlled by DVFS
 - VI's maxim working clock freq is 300MHz
 - Change VI clock divider from an integer to a decimal, so the
   maxim VI clock on Cardhu should be 272MHz (PLL_P is 408MHz and
   divider is 1.5)

Bug 1478352

Change-Id: I4028ed8531d92300d131befb53a4c9dc9f90930d
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/419071
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>
video: tegra: nvhost: validate nvmap_handle_ref

nvhost_job_unpin should always get the nvmap_handle_ref
from rb_entry after validating handle and presence
in the tree.

Bug 1478467

Change-Id: Ibf5f64a1a82fea8adbf7500bdb36b76357776448
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/436076
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
video: tegra: host: power module before access

There could be race in refcount update leading to
access of module registers without enabling the clock
and power.This patch tries to catch such instances
and enables power.

Bug 1478467

Change-Id: Ia32da44bfcd7838e312815b6261ccadf4470a761
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/448701
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
media: tegra_v4l2_camera: use FRAME_START syncpt

Also use nvhost_syncpt_incr_max_ext().

Bug 1478352

Change-Id: Ib868bd2bd7a070e4c410e48bd51977ac45b7d477
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/439471
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
nvmap: fix test condition to avoid infinite loop

Make sure that we dont enter infinite loop due to
negative value of pins in some cases. Also remove
debugging check for refcount.

Bug 1478467

Change-Id: I7df8efa5b3cf8927a0c18363add4f031aca48e48
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/450209
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
arm: tegra3: PCIe Clock and Reset Conform to Specification

PCIe Reset line must be asserted for at least 100us after clock is enabled.
PEX 2 Controller Register fix, offsets are not at constant intervals.

Bug 1521306

Reviewed-on: http://git-master/r/225399
(cherry picked from commit df0760bf515236bed2e87e590509642ab72a01b5)
Change-Id: I7b44ea51e7e02f2bca93cfc75ed85e01ab91fe03
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/435598
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arm: tegra30: pcie: do not disable clk after deasserting resets

Do not disable and re-enable clocks after deasserting
PCIE, AFI and PCIEX resets. Deasserting the resets should
be followed by programming the PCIE.

Bug 1521306

Change-Id: Idc43bc9b21cac3818852ed059fe512f4cd75b748
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/495616
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>