hdl/*/*/generated/virtex6/*: (2/4) back to parallel CORDIC for ease timing

The 35 and 1120 clock enables would give plenty
of time for TBT and FOFB CORDICs to stabilize,
easing timing closure
scripts/*: (3/4) update scripts to reflect recent changes

This reflect the changes made in commit bbe6c9b64:

* Removed FIFO before each Divider Core. Now, we are using
  a simple upsampling + pulse stretcher

* Using 8 Clock per division in all Divider Cores

* Increase transition bandwidth of TBT filter

* Decrease number of coefficients from more than 800 to
  around 240.

* Using 3 CIC sections instead of 5 for all rates

* Changed from Parellel CORDIC to a complete Serial

* Using Embedded  Multiplier for Compensation In CORDIC

* Using Mults in all Kx, Ky and Ksums

* Fix wrong cast in FOFB rate
hdl/*/*/generated/artix7/*: (4/4) back to parallel CORDIC for ease timing

The 35 and 1120 clock enables would give plenty
of time for TBT and FOFB CORDICs to stabilize,
easing timing closure