First commit of testbench generator script

Doesnt currently extract signals from the DUT port list. This
is a feature to be added!
 On branch feature/tbgen
 Changes to be committed:
   (use "git reset HEAD <file>..." to unstage)

	new file:   src/testbench_template.vhd
	new file:   tools/tbgen.py
Can now extract component declaration
Added automatically generated testbenches for unverified modules.
 On branch feature/modules
 Changes to be committed:
   (use "git reset HEAD <file>..." to unstage)

	new file:   src/test/ff_jk_tb.vhd
	new file:   src/test/mux_2to1_tb.vhd
	new file:   src/test/mux_4to1_tb.vhd