Added payload address tables and connection file for the mini LUT-simulation FWs.
Added different classes for the different access modes for luts. Added separate test scripts for common addresses and asymmetric LUTs
Changed TEST_INSTRUCTIONS to point to Twiki with notes / docu.
Added class that parses json-based lut data and test script with test-json.
Merge pull request #3 from dinyar/master

Constraints gen script, removed VHDL code
Merge pull request #3 from jlingema/master

Merge recent changes.