Added multiple modules, initial architecture change

Subsequent changes are aimed at adopting a more modular approach, with a
structural architecture based on independent FSM and datapath.

- Added ALU control unit
- Added register file to support general registers rather than through
internal signals in the processor description
- Split memory into instruction memory and data memory
- Added concurrent read/write access to data memory
- Added multiplexer 2-to-1
- Adapted testebenches to changes