fcl-db: bufdataset: formatting

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@26601 3ad0048d-3df7-0310-abae-a5850022a9f2
Handle LDRD and STRD correctly in RegInInstruction for ARM

LDRD and STRD only have the first even numbered register in their instruction operands,
this additional code will also check for the register following it.
Example:
  ldrd r0, [r13]

The old code will only detect r0 as in use, not the implicit r1.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@26602 3ad0048d-3df7-0310-abae-a5850022a9f2
Add MovLdr2Ldr peephole optimizer for ARM

The existing LdrLdr2LdrMov optimizer will generate a lot of
sequences like this:

ldr regA, [...]
mov regB, regA
ldr regB, [regB, ...]

this now gets changed to

ldr regA, [...]
ldr regB, [regA, ...]

this saves an instruction and might open up more possibilities for the load scheduler.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@26603 3ad0048d-3df7-0310-abae-a5850022a9f2