rmodule: add subsections to linker script

Depending on the compiler options, subsections of the form
of .section.subsection could be generated. Therefore, include
those subsections for .bss, .sbss, and .data.

Change-Id: I80dd64d8c62e7bc449ee2bbc0a22a941777e2ea6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5407
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
drivers/elog: Fix implicit function declaration issue

Fix compilation. Relying on the pre-processor to condition an if
statement will lead to warnings of implicitly defined functions. To
solve this dilemma add symbols to resolve to at compile time.

Change-Id: Id0117528c5579cc1dec750a8a17a76fab4314b3f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5504
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
mainboard: New port Packard Bell LM85.

Change-Id: I8c1548470c605d06825fe35579879e806bf33542
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5271
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS

Match the definition of NODE_PCI() with get_node_pci(), so romstage
and ramstage agree of the PCI BDFs for nodes.

Note that all board have CONFIG_CDB = 0x18 and the maximum for
nodes = 8, so we always have (CONFIG_CDB + x) < 32.

Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5536
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
amd/torpedo: Remove unused Kconfig options

These are not used with cimx/sb900 vendorcode.

Change-Id: I489ee80c739b31edac649491497162c65316996e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5537
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS

All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1.

Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5538
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS

Following boards use cimx/sb700:
  amd/dinar
  supermicro/h8qgi
  supermicro/h8scm
  tyan/s8226

Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).

Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
Together with documented 4-bit restriction for APIC ID field, this APIC ID
programming matches with MP tables and ACPI tables.

I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
we do not have in the tree.

Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5539
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Move MAX_PHYSICAL_CPUS to AMD k8 and fam10

This was always AMD-only and it was never properly used with AGESA.

Change-Id: Ifb461ee845e442f6cf90aca52470cfb66e862bfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5540
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file

These definitions were scattered in a couple of files, and we risk
scattering them all over the place. Provide a common file for these
definitions.

Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5547
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping table

Each GEVENT pins can be mapped to a specific GPE via the SCI map.
The default mapping is not appropriate for this laptop, so use the
AGESA functionality to map currently known events.

Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5548
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPI

This patch completes ACPI support for the lid switch. The lid SCI now
notifies the OSPM of the status change when the lid is closed or
opened, allowing system to suspend. The wake source is also declares,
and the system wakes when the lid is opened.

The system resumes successfully, but the display still does not come
back on.

Change-Id: I803c4fc64e15f8d1a90791ec246af66604646d8b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5549
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
southbridge/amd/agesa/hudson: Refactor SPI controller driver

The SPI controller driver used numerical offsets to access SPI
registers, making it unreadable without the datasheet. Use less magic
and more #defines to improve readability.

Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5557
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
southbridge/hudson: Remove redundant definitions of ACPI IO ports

The ACPI IO ports were defined twice, and used inconsistently. Only
keep one of the definitions for consistency.

Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resume

It's not needed, and puts the EC back into APM mode. The EC does not
shut down during S3 sleep, so we don't need to re-initialize it.
Lid SMI will have been disabled in the switch to ACPI mode, don't
re-enable it.

Change-Id: I2c06df140f63427dac32ae095d29e68f64135358
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5555
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
AMD hudson and yangtze boards: Let mainboard declare power button

The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and
always had the wake source declared as GPE3. This is not the correct
wake source for all boards. On some laptops declaring a wake source is
not needed, as the wake mechanism is handled by the EC.

Move the declaration of the power button to mainboard ASL files, and
scope it as \_SB.PWRB . This also makes the naming consistent with the
examples in the ACPI spec. The wake source for the PWRB of HP Pavilion
M6 1035dx is removed, as it is incorrect.

Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11

Hudson ASL files assume the USB power event notifications are mapped
to GPE 0xb. Since that GPE is not used on this board, map these events
to GPE11. This GPE is already handled in ACPI via Method(_L0B). We
adjust this method to also notify the XHCI controller at PCI 10:0.

Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18

The PCIE PME pin from the APU is connected to GEVENT8, but the
northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
accordingly.

Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
southbridge/hudson: Initialize ACPI IO ports separate of FADT

The ACPI IO ports, and the respective SMI (for HAVE_SMI_HANDLER), were
initialized when the FADT table was written. This works well on a cold
boot, but the ACPI ports are not initialized on S3 resume, as ACPI
tables are not written. This will not work on S3 resume if the default
ports are not what we set them, or if AGESA sets them to some other
value.

To solve this, move the port configuration to southbridge chip init.

Change-Id: Ib4043f0fa5e20f08d320acd12ce84d4d789cd035
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
southbridge/hudson: Disable USB controllers if devicetree says so

Change-Id: I009a01d3324d48d2eeda87d74c8e3e7c27958ee2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
usbdebug: Reduce bus reset delays

According to EHCI specification, host controller software stops
the USB Reset condition by writing PORT_RESET=0. Software then
poll-waits this bit until controller hardware has completed USB
Reset sequence and read returns with PORT_RESET==0.

Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>