msm: mdss: prevent dereferencing of user space pointer

We were dereferencing a userspace pointer in kernel.

Change-Id: I128455904cd396690350fc6b784a8844d594539c
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
ARM: dts: mdss: Add boolean property for LUT readability

LUT read is not supported by hardware in the case of msm8226.
Adding property to dtsi file to denote the absense of support
for read in hardware.

Change-Id: I29cf869af4135e1199bc0feb4369700b994520ec
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Reading IGC and PGC LUT from cached values

Certain targets like msm8226 do not have capability of reading
IGC and PGC LUT from hardware registers.
Adding functions to read the LUT values from software cache.

Change-Id: Ifd0f5f131b7ff1fd7d1fb122425241a0e0cec328
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Hold MDP clock Ref count in pan_display path

If handoff fails, the clock ref count becomes 0 and iommu
will get detached. In pan display path, since at that
particular instant iommu gets detached, we use physical
address. After this if iommu is again attached and physical
address is fetched, it can result in continuous IOMMU page
faults. To address this hold MDP clock ref count
in pan display path.

Change-Id: I2370b276acdced2cf22083eb80fcad1b2e454315
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
msm: mdss: Fix incorrect fbc parameter bit offset

Fix bit offset for lossy RGB threshold in the lossy mode
FBC register. This fixes incorrect fbc parameters being set.

Change-Id: I5e772cc1a8244bad8a236dca561552c4eb516d98
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
msm: mdss: Correctly calculate DSI clocks if fbc is enabled

In cases where frame-buffer compression(fbc) is enabled, the
compressed ratio for xres isn't considered. Add logic to correctly
account for fbc when needed.

Change-Id: I0eec90cbbe0a0ffaea94cf1c2d6231e6545403b6
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
msm: mdss: Consider FLIP flags while optimizing pixel fetch

While calculating source and destination rect of a pipe for the
programmed ROI, consider FLIP flags set for the pipe.

Change-Id: I631453c26f443b08a23556f83195d9914e05b41d
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
video: mdss: Update fence error handling

Change-Id: I954e3bcdd89453e1d58048caf69510049d7ae42e
mdss: dsi: Don't make lack of reset GPIO a fatal failure yet

* mdss_dsi_request_gpios will make this a fatal failure later
  regardless.
* Also fix a error string copy paste error.

Change-Id: I7e49f5b547277a758e3b153dba1be43b46a1e774
msm: mdss: Change notify_update ioctl copy size to match ioctl definition

The MSMFB_NOTIFY_UPDATE ioctl is defined based on sizeof(unsigned int).
However, we use the incorrect size when copying to and from userspace.
The sizes for copying have been fixed to match the ioctl definition.

Change-Id: I0f63228e5b4ad936d89c5f2bcbd84204037a0edf
Signed-off-by: Benet Clark <benetc@codeaurora.org>
msm: mdss: Use correct error checking for mdss bus scale register

Previously, we were checking the error value for mdss bus_scale_register
incorrectly. Now we check the error value for null rather than a negative
value.

Change-Id: If7fda0584df82d6c007829f2e63af9b735cafb7e
Signed-off-by: Benet Clark <benetc@codeaurora.org>
msm: mdss: provide an exclusive access to QSEED2 block

Calibration tool and pp module uses the QSEED2 block on
VIG pipe to set the sharpness. This sharpness effect
is overwritten when both modules tries to update it
at the same time. Hence, it is required to provide
an exclusive access to QSEED2 block when target is in
display tuning mode.

Change-Id: I41b85313e529a3cca70de7e652c3abb7d4defbca
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
msm: mdss: provide an exclusive access to SSPP op_mode

IGC/SPA/QSEED effects are supported by PP module and
calibration service. User is not able observe the effect
when both modules try to enable/disable the effect
at the same time. This change provides calibration
service an exclusive access to SSPP_SRC_OP_MODE on
all source pipes and VIG_OP_MODE on all VIG pipes
during tuning state.

Change-Id: Ice50f579fcb900f673c52a6b17f40aeb3a0e0a66
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
msm: mdss: update layer mixer access for calibration tool

Calibration tool should have register access on all layer
mixers connected to DSPP pipe and WB path. It should
also have control layer register access to read
the current layer mixer configuration.

Change-Id: If2cc86c2e6f470e090746a400b16cb540948c3e9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
msm: mdss: fix pp setup on SSPP pipe in rotation scenario

mfd is not updated on controller when pipe is setup
for rotation scenario. However, post processing module
check it for all use cases that leads to pp update
failure SSPP pipe. This change avoids the extra checking
and allows pp module to update SSPP pipe in all use
case scenarios.

Change-Id: I8718e67ca49067c9af7b492da7cdb1344e826389
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
msm: mdss: Fix DTM state entry check in pp module

DTM state should be updated if framebuffer structure
is accessible for the pipe. Wrong check fails the
DTM state update and does not provide an exclusive
access to PP blocks on SSPP.

Change-Id: I170182c2d59c5f09d1cb911f61f3e0a1af91b067
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
msm: mdss: add proper pipe unmap calls for pipe references

For every pipe get/map call there needs to be a related unmap call.
These are missing in some cases.

Change-Id: I85f8897be6d34ef217102ef922a48afb6e6cc838
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
msm: mdss: Add core clock level selection in MDSS

Currently core clock is calculated for each frame and
depending upon the calculated value clock driver rounds it
to the nearest clock level from clock table. Now do
quantization of required clock rate at mdp driver itself
once before the request goes to clock driver.

Change-Id: Ie30947fb8f7d2978bb121b28920c05888332bf3f
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
video: mdss: Sync with upstream

video: mdss: Cleanup stray XLOG statements

Change-Id: I5a44f297225dae1f207933ae4b51f896e956fc3d

Revert "msm: mdss: fix MDP color format offsets"

This reverts commit 71745202387328d6a73b1d7c5b9c5e4bc41108ff.

msm: mdss: remove panel type check for split display case.

Split display flag is derived from dsi controller configuration
specified at dtsi. Therefore no need to add checking panel
type at FB registration.

Change-Id: I5b60656c1f5724bdc358d743b8d7600d5beba0b3
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>

Revert "msm: mdss: Introduce MDP REG base offset"

This reverts commit e9019c39a4d59b0c91e9a9ff789048bc2488dad0.

Change-Id: Idb6ecc35bad68f0bca2864965936234e57aa9d4e

msm: mdss: MDP clock optimization for single layer video playback

MDP core clock bumping is not required for single layer video
playback in 8x26 targets. Hence add revision check to avoid fudge
factor.

Change-Id: I1b0ccb4ef50514f705845b0218fa6ca0d28c1779
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>

Revert "msm: mdss: remove obsolete method of mixer register read/writes"

This reverts commit 2f83cec1aa11bd9f33725e3d9fc1fdd1cb2f15e9.

msm: mdss: enable under-run interrupt for secondary ctl

In split-display use-cases two ctl paths are active but one acts as
master and other as secondary. Currently under-run interrupt is only
enabled for master ctl. Enable under-run interrupt for secondary ctl
for seamless tracking.

Change-Id: I849419c4077fed384431079952027149c31b33fc
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>

msm: mdss: enable overlay handoff for secondary ctl on split display

When split display is enabled, two control paths are active. Currently
only primary ctl path is handed off in overlay handoff. Extend this
handoff to secondary ctl path when split display panel is connected.

Change-Id: If071f8f0886c811b46c574529526b40e55351409
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>

Revert "msm: mdss: Enable dynamic clock gating for MDSS AHB clock"

This reverts commit 57b1b09db2ebf5ad9391fa8d27973c47f25d7a55.

msm: mdss: restrict decimation when layer format is macro-tile

When layer format is macro-tile, decimation cannot be supported. Add the
necessary checks to fail HW configuration for such use-case.

Change-Id: I68adbcdf8014f9ad528e945928f309b221c6dcfd
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>

video: msm: Remove double iommu attach in rotator

Change-Id: I0aadfc213c249b8780aa260f1d80b070ba4e9857

video: mdss: Cleanup after merge

Change-Id: I01507248309b2156a36c65628c4ccd5aad11e8f0

Revert "msm8974: Set correct clock offsets in DT"

This reverts commit ceeaad4da70d2fdd62a9fb7f9d53b9322e0b07b0.

video: msm: More cleanups

Change-Id: Icf8b97d1382947df83c9c316a8e8ad49fbae3ab7

Revert "msm: mdss: add bandwidth check per pipe"

This reverts commit 8a2cf4caafa905b83ac5d81ec7e2704f3d6ae825.

Change-Id: I060e674e6651d615e944d22a01c340e8d0277fe5

Revert "msm: mdss: adjust command mode bandwidth with hblank factor"

This reverts commit 2311a289c2961180ffcbf9647af26ed942085df4.

Revert "msm: mdss: enable synchronous flush only for video mode panels"

This reverts commit 8842e29a5fc7a8eab09e25bb096ef79ce20641df.

Conflicts:
	drivers/video/msm/mdss/mdss_mdp_ctl.c

Change-Id: I09248da163362aa0643ba1d58782333eab991444

video: mdss: Even more cleanups

Change-Id: Ie5afaabf6e94007642fd6c0f6bb6dfa2f9f0d2c4

Conflicts:
	drivers/video/msm/mdss/mdss_dsi_host.c
	drivers/video/msm/mdss/mdss_mdp_ctl.c
	drivers/video/msm/mdss/mdss_mdp_intf_video.c
msm: mdss: add support for rotator in mdss_mdp_mixer_get

Currently ctl->mfd is not populated for rotator sessions. If
mdss_mdp_mixer_get is called by rotator session then it will always
fail the NULL check for ctl->mfd. This will flood the logs for every
rotator commit and can lead to un-predictable outcome. Fix this by
properly handling rotator case in mdss_mdp_mixer_get.

Change-Id: Ib1896149302bd60b99028ae26df2393fab30dd6e
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>