Fix indentation of property/endproperty around pre-processor directives.

	* verilog-mode.el (verilog-beg-of-statement)
	(verilog-preprocessor-re): Fix indentation of property/endproperty
	around pre-processor directives.  Reported by Alex Reed.
Fix electric tab deleting form-feeds.

	* verilog-mode.el (verilog-do-indent): Fix electric tab deleting
	form-feeds.  Note caused by indent-line-to deleting tabls pre
	24.5.