msm: kgsl: Do not detect faults when GPU core is idle

Do not detect GPU faults when GPU hardware status is idle,
this leads to incorrect fault detection.

Conflicts:
	drivers/gpu/msm/adreno.h

Change-Id: I7a9f8c49eb819241698f99fd50aaed400aadd4f4
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Protect fault detect start with active count

Get the active count when enabling GFT from sysfs so the performance
counters can be properly programmed.

CRs-Fixed: 622252
Change-Id: Ic0dedbadfe56f8c66aca15fb521494a2fc00332b
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: get pm_qos_latency from device tree

pm_qos_latency parameter can be configured from
device tree as well. Will set to default value if
entry not found in target device tree.

Conflicts:
	include/linux/msm_kgsl.h

Change-Id: I76271f4fdc26e191431e5dfe2a6de9e2b3ab426f
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
msm: kgsl: change pm_qos_latency to pm-qos-latency

Use hyphen symbol instead of underscore for pm-qos-latency
property name. Hyphen should be used instead of underscore
in device tree property name.

Change-Id: I23f720159b4ecb3d81cbd13b570cee8fc633253a
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
msm: kgsl: Protect CP_STATE_DEBUG_INDEX

Put CP_STATE_DEBUG_INDEX and CP_STATE_DEBUG_DATA under protection
to keep it from being written from an IB1. Doing so however opens
up a subtle "feature" in the microcode: memory read opcodes turn off
protected mode in the microcode to do the read and then turns it
back on regardless of the initial state. This is a problem if the
memory read happens while protected mode is turned off and then we
try to access a protected register which then complains and goes boom.

To account for this irregularity explicitly turn back off protected
mode in all the places where we know this will be a problem.

Change-Id: Ic0dedbad1397ca9b80132241ac006560a615e042
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Add new API's to track device mutex owner

Add new API's kgsl_mutex_lock/unlock to track device mutex owner.
Mutex owner is an atomic variable and all operations set/clear on
it are also atomic to avoid any race conditions.

If a thread tries to acquire the mutex using new API, try to acquire
the mutex only if mutex owner is not same as current thread. This is
to prevent deadlocks which can happen if a thread tries to acquire
mutex with mutex held.

Change-Id: I3da4d0427ede5458f6a663043c57a4799b72d8fd
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>

Conflicts:

	drivers/gpu/msm/kgsl_device.h
	drivers/gpu/msm/kgsl_iommu.c
msm: kgsl: Add hang interrupt and change HW fault generation

Add a sysfs property to dynamically control HW hang interrupt.
HW fault is generated for hang interrupt only.

Change-Id: Ib50c57476e54cccfef0ae18a0cbb42fce29457c1
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
msm: kgsl: Enable hang interrupt for a330v2

Enable hang interrupt for a330v2 by default during
GPU initialization.

Change-Id: I0dd2054b8d640cf3b17afd3e2f8c4b88d575fce2
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
msm: kgsl: Update calculation for graphics IOMMU context IDs

Calculate graphics IOMMU context IDs using the 'label' property of
the device tree node of that context. Context IDs are independent
of the register addresses of the SMMU device and its contexts, which
change for every target.

Change-Id: I16825d7248081997a442d4fb59ca5b04b88e33fd
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>
Signed-off-by: Prabhat Awasthi <pawasthi@codeaurora.org>
msm: kgsl: Do not return invalid power stats when the device is off

adreno_power_stats() was returning unitialized data when the device
state was not active. Leave early from the function if the device
is not active and return 0s instead.

Change-Id: Ic0dedbadf6201cadb4472327c4ce7f9d9d32b82d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Prabhat Awasthi <pawasthi@codeaurora.org>
MSM8974: Fix build errors/warnings:

Change-Id: Ia851b2dea8e353db6231cfd1abfd535d49e03b7a
msm: mdss: Add lcd notifier
Keep my name on my work.
msm: krait: add CPU Voltage control.

Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
lib/memcopy: use glibc version

the kernel's memcpy and memmove is very inefficient. But the glibc version is
quite fast, in some cases it is 10 times faster than the kernel version. So I
introduce some memory copy macros and functions of the glibc to improve the
kernel version's performance.

The strategy of the memory functions is:
1. Copy bytes until the destination pointer is aligned.
2. Copy words in unrolled loops.  If the source and destination are not
   aligned in the same way, use word memory operations, but shift and merge
   two read words before writing.
3. Copy the few remaining bytes.

Signed-off-by: Miao Xie <miaox*******>
Signed-off-by: faux123 <reioux@gmail.com>
lib/string: use glibc version

the performance of memcpy and memmove of the general version is very
inefficient, this patch improved them.

Signed-off-by: Miao Xie <miaox*******>
Signed-off-by: faux123 <reioux@gmail.com>
msm: Fix high load average from uninterruptible waits

 * The load average on all MSMs is currently hovering at around 14
   due to uninterruptible waits in various places.
 * Convert these waits to interruptible waits to bring the load
   back down to zero at idle.

Change-Id: I14bad4af135b1594e235e2252cb484cb34d91054

Conflicts:
	drivers/thermal/msm_thermal.c
cpufreq: Manage only online cpus

cpufreq core doesn't manage offline cpus and if driver->init() has returned
mask including offline cpus, it may result in unwanted behavior by cpufreq core
or governors.

We need to get only online cpus in this mask. There are two places to fix this
mask, cpufreq core and cpufreq driver. It makes sense to do this at common place
and hence is done in core.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
msm8974: Adapt memutils optimizations from msm8960pro

Preload farther to take advantage of the memory bus, and assume
64-byte cache lines.  Unroll some pairs of ldm/stm as well, for
unexplainable reasons.

Future enhancements should include,

- #define for how far to preload, possibly defined separately for
  memcpy, copy_*_user
- Tuning for misaligned buffers
- Tuning for memmove
- Tuning for small buffers
- Understanding mechanism behind ldm/stm unroll causing some gains
  in copy_to_user

BASELINE (msm8960pro):
======================================================================
memcpy 1000MB at 5MB       : took 808850 usec, bandwidth 1236.236 MB/s
copy_to_user 1000MB at 5MB : took 810071 usec, bandwidth 1234.234 MB/s
copy_from_user 1000MB at 5M: took 942926 usec, bandwidth 1060.060 MB/s
memmove 1000GB at 5MB      : took 848588 usec, bandwidth 1178.178 MB/s
copy_to_user 1000GB at 4kB : took 847916 usec, bandwidth 1179.179 MB/s
copy_from_user 1000GB at 4k: took 935113 usec, bandwidth 1069.069 MB/s
copy_page 1000GB at 4kB    : took 779459 usec, bandwidth 1282.282 MB/s

THIS PATCH:
======================================================================
memcpy 1000MB at 5MB       : took 346223 usec, bandwidth 2888.888 MB/s
copy_to_user 1000MB at 5MB : took 348084 usec, bandwidth 2872.872 MB/s
copy_from_user 1000MB at 5M: took 348176 usec, bandwidth 2872.872 MB/s
memmove 1000GB at 5MB      : took 348267 usec, bandwidth 2871.871 MB/s
copy_to_user 1000GB at 4kB : took 377018 usec, bandwidth 2652.652 MB/s
copy_from_user 1000GB at 4k: took 371829 usec, bandwidth 2689.689 MB/s
copy_page 1000GB at 4kB    : took 383763 usec, bandwidth 2605.605 MB/s

Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>

Conflicts:
	arch/arm/mach-msm/Kconfig
	arch/arm/mach-msm/Makefile

Conflicts:

	arch/arm/mach-msm/Kconfig
arch: arm: lib: optimize memcpy for cortex-A15

The LDRD/STRD instruction is faster than LDM/STM on Cortex-A15.
Also optimized preload cache size for Cortex-A15.

Added USE_LDRDSTRD_OVER_LDMSTM to turn on LDRD/STRD optimization.
Added ARM_PLD_SIZE, default 32. Should set to 64 for Cortex-A15.

Bug 1185248

Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>