Add better decoding support for Haswell server processors

Software developer manual rev 052 released in September 2014
provides more detail on the MSCOD values for PCU, QPI and IMC banks.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
More compact data structures for reporting SNB/IVB memory controller errors

While working on Haswell server support we cloned ivy-bridge.c as
a base - and then noticed that the tables to report MSCOD values
in memory controller banks did not report correctly when more than
one bit was set in the field, so converted it to use SBITFIELD()
entries for each bit.

It isn't clear whether Sandy Bridge or Ivy Bridge will ever report
more than one bit set in their memory controller MSCOD fields - but
it is worth converting them too for a more compact representation.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Update some Xeon CPU names to official names

Signed-off-by: Andi Kleen <ak@linux.intel.com>