x86: Prevent getting stuck while trying to clear the APIC

If some interrupt source (typically a level-triggered IOAPIC pin)
continuously sends messages to the APIC we are trying to clear from
pending bits in ISR and IRR, we will get stuck in the hypervisor in an
interrupt storm.

Avoid this by limiting the number of handled interrupts to the number of
vectors we have. When reaching this limit, simply raise TPR to break out
of the loop. It's cleared again on exit from apic_clear, and the code
booting the CPU can handle the then pending interrupt itself. That's
just like real hardware would behave.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Refactor x2apic_handle_read/write

Use the relative APIC registers number internally and prepare the
interface of x2apic_handle_write for returning access errors.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Move ICR access dispatching into x2apic_handle_write

More code sharing, specifically when AMD support will be added.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Filter writes to reserved APIC register bits

Set up a bitmap for all xAPIC/x2APIC register that marks reserved bits
(or complete registers). Check to-be-written values against this bitmap
before executing accesses in hypervisor context.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Filter LVT delivery modes

Do not allow cells to program anything else than Fixed or NMI mode. NMIs
will still be swallowed by the hypervisor NMI interception path, so perf
& Co. remain broken.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Update TODO

Recently added APIC topics are addressed now.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
inmates: pci-demo: Clear STATESTS before triggering the MSI

STATESTS may still have pending events which could prevent a MSI
delivery after controller reset. That reset doesn't clear them, so do
this explicitly.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
configs: Adjust MSI capability address of HDA devices

Real hardware locates MSI at 0x60, only current QEMU has this at 0x50
(patch posted).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>