libpayload: Update defconfigs

Update x86 and ARM defconfig. Adds default N to specific timer
and serial drivers.

Change-Id: Ida6b953565dc6053729c2a72c6342d86596c599b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7449
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
libpayload: Remove config.panther

config.panther was added in a chromium upstream patch. We don't
want mainboard specific configs in libpayload, so remove it.

Change-Id: Ibfb894a0262911c13e88bc161749b78e2b5c5185
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7450
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
libpayload: usb: Fix up usb_shutdown() code paths

This patch combines a few minor fixes and refactoring to the various
host controller and root hub drivers to ensure they all do the right
thing on a call to usb_exit(). It puts a usb_detach_device(0) call
into detach_controller() so that the HCD doesn't need to remember to
tear down the root hub itself, and makes sure all root hubs properly
detach the subtree of devices connected to their ports first (as
generic_hub and by extension XHCI had already been doing).

It also fixes up some missing free() calls and replaces most 'ptr =
malloc(); if (!ptr) fatal()' idioms with the new x(z)alloc().

BUG=chromium:343415
TEST=Tested EHCI on Big and OHCI, EHCI, and XHCI on Snow. Could not test
UHCI (unless anyone volunteers to port coreboot to a ZGB? ;) ), but the
changes are really tame.

Original-Change-Id: I6eca51ff2685d0946fe4267ad7d3ec48ad7fc510
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193731
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 5791b546e5a21a360d0c65888a5b92d5f48f8178)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I00138f0aeceb12ed721f7368c7788c9b6bee227d
Reviewed-on: http://review.coreboot.org/7222
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
libpayload: usb: Remove automatic clear_stall() calls from transfers

We've recently fixed a problem where an external hard drive would choke
due to one too many CLEAR_FEATURE(HALT) commands in the XHCI stack with
"libpayload: usb: xhci: Fix STALL endpoint handling". Clearing stall
conditions from within the transfer function is wrong in general... this
is really something that is host controller agnostic and should be left
to the higher-level driver to decide. The mass storage driver (the only
one that should really encounter stalls right now) already contains the
proper amount of clear_stall() calls... any more than that is redundant
and as we found out potentially dangerous.

This patch removes automatic clear stalls from UHCI and OHCI drivers as
well to make things consistent between host controllers.

BUG=chromium:192866
TEST=None. I could borrow the original hard drive from Shawn and compile
a Snow to only use the OHCI driver to reproduce/verify this, but alas, I
am lazy (and it's really not that important).

Original-Change-Id: Ie1e4d4d2d70fa4abf8b4dabd33b10d6d4012048a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193732
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit d46e183f3e7e0b0130becdefa6fd3ef8097df54b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie8f4ab3db8ec0d9a2d1e91c62967833e59c46700
Reviewed-on: http://review.coreboot.org/7223
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
libpayload: timer: Move the timer drivers from depthcharge to libpayload.

These drivers are needed right away and never really fit into depthcharge's
driver model anyway.

CQ-DEPEND=CL:194064
BUG=None
TEST=Built and booted nyan, link, and peach_pit and verified that timer values
in cbmem were reasonable. Built for nyan_big, nyan_blaze and daisy.
BRANCH=None

Original-Change-Id: Ia7953cfece57524262a6c7d6537082af7a00f4d6
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194058
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit f30a410f0a248c93bc34f5868af1596bf8ce3cdd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I782d20f3cd63210a87c712643c7a53753f5ef301
Reviewed-on: http://review.coreboot.org/7225
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
libpayload: Add minimal support for PL011 UART

This creates a new PL011 config variable which avoids the
infinite busy wait on serial_putchar() because the register
mapping is not compatible with current implementation.

BUG=None
BRANCH=none
TEST=printf() works on the PL011 based ARMv8 foundation model

Original-Change-Id: I9feda35a50a3488fc504d1561444161e0889deda
Original-Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/187020
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 85779a34a161c324cc8af995ada4393137275f20)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Conflicts:
	payloads/libpayload/Config.in
	payloads/libpayload/drivers/serial.c

Change-Id: I23c8b3728cd7d2d7692b3e86a679e061e88f7bb5
Reviewed-on: http://review.coreboot.org/7422
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
nyan: big: Check dram_end when setting up caching in ROM stage.

When setting up caching on nyan and big, we would set the region after DRAM to
the end of the address space as uncachable. DRAM may actually extend beyond
the end of the address space, so that may result in address aliasing or other
problems. This change adds a check to make sure there's actually space there.

BUG=None
TEST=Built for big.
BRANCH=None

Original-Change-Id: Ic0a98550222f9dfc0aeafd67a2dd1c0c8f4ece44
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/186769
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1866a4d2a001beb97779b611b8b69c63175048f4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If1ca8b5bd4efab8962e03c0d9eaa70c0327ea6b5
Reviewed-on: http://review.coreboot.org/7405
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
nyan: Add 4GB bct support

Replace sdram entry 1 with valid configurations since nyan 4GB board uses
RAM_CODE 1.

BUG=none
TEST=Flash and boot new image.bin. Console shows "RAMCODE=1" and
	"Total SDRAM (MB): 4096"
BRANCH=none

Original-Change-Id: Ia872bd7849f1b58075e1f97bf300e081293cb0d4
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/187450
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit f19e2ea3dd4d314b7540c7cf9a11d7af289d24d0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4914c3811b13c8cee0577101bc0c8ee32a0a5b81
Reviewed-on: http://review.coreboot.org/7406
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
nyan: nyan_big: Mark the address range covering the SRAM as cachable.

The SRAM is very likely faster than going all the way out to DRAM for data,
but I don't think it's part of the cores themselves and won't be as fast as
the L1 caches. Enabling caching for this region reduces the time it takes to
get to the payload by about 75% when serial output is disabled and the main
part of display init is commented out.

BUG=chrome-os-partner:25467
TEST=Built and booted on nyan.
BRANCH=None

Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188459
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e
Reviewed-on: http://review.coreboot.org/7407
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
nyan: Update 924MHz BCT w/latest qual'd cfg, use 924 as default speed for 2GB

BUG=none
BRANCH=nyan
TEST=built and booted coreboot on my Nyan-rev1, browsed, ran Youtube vids,
WebGL experiments, etc. Everything seemed OK.

Original-Change-Id: I877680c9329ed96a0b602f0690acaa12079786d7
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188550
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit b6ca59e9db26f7422fa43ade889c921257a36851)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If166938f241e2a4a8670bfce2df6591b4b71ff67
Reviewed-on: http://review.coreboot.org/7408
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
tegra124: Make the PLLX frequency selectable by model.

The PLLX provides the clock for the main cores which can run at different max
frequencies depending on the specific model of Tegra124. This change makes it
possible to select a model which will, in turn, select a frequency for PLLX.
The default is 2GHz which is the lowest maximum frequency.

BUG=chrome-os-partner:25467
TEST=Booted on nyan rev1. Verified that the selected PLLX frequency was 2GHz.
With a change that selects the right model for nyan, verified that the
corresponding frequency was selected.
BRANCH=None

Original-Change-Id: Iee3a615083dee97ad659ff41cbf867af2a0c325d
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188602
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1282015048420a518e6c6959ce982be70378211a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I448a830f3184ad1afeadbd1c2974c7a27b03a923
Reviewed-on: http://review.coreboot.org/7409
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>