move work for single cycle instructions to following cycle to
improve timing. Means that branches will have to take 2 cycles
even if not taken (was otherwise possible to optimise them down to
one cycle by skipping reading the argument if the branch is not
taken.  but now the flags could be modified in the previous cycle).
try to improve timing by simplifying pipelined register writing
logic.
another go at refactoring single cycle opcodes to try to improve
timing.
remove some CPU provided read-only registers to simplify
read logic.
try to dramatically shallow memory read logic.
begin implementing microcode engine and look up table for
multi-cycle instructions.
refactor microcode out into an explicit memory.
add more missing microcode operations.
add microcode memory to ISE project.