initial
further refactoring
add counter
forgot to commit
forgot to commit for quite a while
add Delay chip
added ADSR generator
again, forgot to commit for a while
finally connected classes to the ugen itself
made sineamp back into a wavetable
renaming source files to less lazy locations
implemented full FM synthesis, finally
added mask bend
making Counter inherit from OutputChip
add adsr generator
added envelope to modulator
separated FMBend into FMBend and FMBendEnv
added clock signal bend
help files
changed gate logic a little