update devIL and dependencies.
Read back CORB/RIRB control register to ensure DMA has stopped

* Spec is somewhat unclear about whether that is really necessary,
  but let's play safe.
Use correct sequence for resetting CORB read pointer

* Spec requires software to wait for hardware to acknowledge the
  reset by waiting for the bit to become set and then manually
  unset it and again wait for it to become unset.
  (cf. HDA spec 1.0a ch. 3.3.21)

* Also, do read-modify-write to protect preserved bits
Preserve reserved bits in registers

* Do read-modify-write cycle to preserve bits marked as RsvdP in the
  following registers: WAKEEN, CORBWP, CORBCTL, CORBSIZE, RIRBWP,
  RINTCNT, RIRBCTL, RIRBSIZE.
Use uncached memory areas if snooping is not possible

* Some chipsets do not support bus-snooping for the HDA data
  transfers. So, when trying to enable snooping, verify that the
  setting was accepted.

* When snooping is not possible, set memory areas for audio buffers,
  buffer descriptor lists and command ring-buffers as uncached to
  ensure memory coherency with the HDA controller.

* This fixes KDLs during booting on some systems where snooping
  is not supported (seen on two systems with AMD chipsets, maybe
  applies to others as well).
  After setting up the buffer descriptor list for a stream, it was a
  gamble whether these writes would be visible to the HDA controller
  when subsequently enabling the stream. On some boots it was unlucky
  and then the HDA controller's DMA engine would go haywire and start
  overwriting random kernel memory with audio input data. The
  scheduler was usually the first victim and caused page fault KDLs
  due to corrupted data structures.