disp/nv50: fix dpms regression on certain boards

Reported in fdo#82527 comment #2.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm: fix regression on original nv50 board

Xorg (and any non-DRM client really) doesn't have permission to directly
touch VRAM on nv50 and up, which the fence code prior to g84 depends on.

It's less invasive to temporarily grant it premission to do so, as it
previously did, than it is to rework fencenv50 to use the VM.  That
will come later on.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm: punt fbcon resume out to a workqueue

Preparation for some runtime pm fixes.  Currently we skip over fbcon
suspend/resume in the runtime path, which causes issues on resume if
fbcon tries to write to the framebuffer before the BAR subdev has
been resumed to restore the BAR1 VM setup.

As we might be woken up via a sysfs connector, we are unable to call
fb_set_suspend() in the resume path as it could make its way down to
a modeset and cause all sorts of locking hilarity.

To solve this, we'll just delay the fbcon resume to a workqueue.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm: make sure display hardware is reinitialised on runtime resume

Linus commit 05c63c2ff23a80b654d6c088ac3ba21628db0173 modified the
runtime suspend/resume paths to skip over display-related tasks to
avoid locking issues on resume.

Unfortunately, this resulted in the display hardware being left in
a partially initialised state, preventing subsequent modesets from
completing.

This commit unifies the (many) suspend/resume paths, bringing back
display (and fbcon) handling in the runtime paths.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
HACK: drm/nouveau: prime: Pin buffer objects to VRAM

This is currently required to work around the lack of proper SMMU
support on Tegra. Ideally buffer objects could always be pinned to GART
and the SMMU will take care of mapping them to a linear I/O virtual
address range for importers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
[HACK] add gk20a instmem

This is a gazillion times faster, but requires to invalidate the
GPU L2 (probably at a better place than this!)
Revert "ltc/gf100-: fix cbc issues on certain boards"

This reverts commit b15a810e97b8279cdbbfc90ede9e3fb51157f92b.

Causes IOMMU errors on GK20A.
drm/nouveau/vm: fix mapping of SG pages list

SG pages lists (not to be confused with scatterlists) are a list of 4KB
memory pages used to define a nouveau_mem. Mapping them to a VM that
does not use 4KB apertures resulted in each subsequent 4KB physical page
being mapped into a larger VM aperture, thus creating an incorrect,
overlapping mapping.

This patch fixes this issue by detecting when such mappings occur and by
skipping the required number of pages in the list to ensure a correct
linear mapping.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: introduce nv_device_is_cpu_coherent()

Add a function allowing us to know whether a device is CPU-coherent,
i.e. accesses performed by the CPU on GPU-mapped buffers will
be immediately visible on the GPU side and vice-versa.

For now, a device is considered to be coherent if it uses the PCI bus on
a non-ARM architecture.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: implement explicitly coherent BOs

Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which
means that we want the allocated BO to be perfectly coherent between the
CPU and GPU. This is useful on non-coherent architectures for which we
do not want to manually sync some rarely-accessed buffers: typically,
fences and pushbuffers.

A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent
architecture will be populated using the DMA API, and accesses to it
performed using the coherent mapping performed by dma_alloc_coherent().

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: synchronize BOs when required

On architectures for which access to GPU memory is non-coherent,
caches need to be flushed and invalidated explicitly when BO control
changes between CPU and GPU.

This patch adds buffer synchronization functions which invokes the
correct API (PCI or DMA) to ensure synchronization is effective.

Based on the TTM DMA cache helper patches by Lucas Stach.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: allocate GPFIFOs and fences coherently

Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to
allow them to be safely accessed by the kernel without being synced
on non-coherent architectures.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Revert "drm/nouveau/vm: fix mapping of SG pages list"

This reverts commit 8479bab3dabf349693e9c5716109a6d441b9d510.
Experiments with large pages
graph/nvc0: add support for netlist firmwares

NVIDIA is releasing some GPU firmwares for the Tegra SoCs under
linux-firmware. The release format is a single file (called a netlist)
containing all the firmwares relevant to a GPU, which must thus be
extracted. This patch adds support for parsing the netlist and loading
the firmwares for the NVC0 family of GPUs, falling back to the previous
firmware lookup method is no netlist was already loaded.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
platform: support for netlist firmwares

Netlists released by NVIDIA are made of a single file containing
firmwares that can potentially be used across different engines. It
therefore makes most sense to load a netlist once before engines are
probed and have them duplicate their firmwares so the netlist can
be freed at the end of probe.

This patch implements this mechanism and adds the lookup data for GK20A.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>