bootrom: wait more than SD_NCR cycles for data start token.

I have noticed that with some SD cards the data start token can take
much more than 8 cycles for data to arrive at higher clock rates.  Use a
larger delay and increase the clock speed for much quicker boots.
rtl/debug: increase the reset counter size.

256 cycles is dangerously close to the bare minimum required to reset
caches.
rtl/fpga: wire up a second SPI port.

Add a second SPI port for connecting an ENC28J60.  This uses the same
SPI master, but use separate MISO, CLK, NCS pins etc for easier
connection to the headers on the DE0 nano.