reduced frequency of clk_s and clk_g, Tau in Observer_testbench is 10 euqal to TOP.vhd
Reset the improvement caused by inducing enable_logic as an register
this results to fmax for Observer(inclk:100Mhz):109,48Mhz and
fmax for Signalgenerator(inclk:50Mhz):95,57Mhz

Some more improvements for Observer_behave made:
-) elsif(enable_logic='1') branch is useless, so i reduced it to the lower branches
Observer(inclk:100Mhz):115,77Mhz
Signalgenerator(inclk:50Mhz):98,14Mhz
-) in Observer Behave was an error
-) changed behaviour of Observer, so that output will be only
changed on the next clock edge
this changed inmproved the design, it shows
an incorrect behaviour in the simulation, but a correct behaviour on
the logicanalysator
it seems that the output change happens before the clock edge ??

-) testet only with one observer
all tests included that signalgenerator and observer are driven with the same
clock frequency