CPLD version 1.2

Moved IOPAGE from $02xx to $C0xx
Reordering of SYSCONF and INOUTP control bits
Renamed SDPORT to SDDATA
New SDDATA update mechanism (SR FF)
Corrected SPI bit shift order (MSB shifts first)
Implemented two SPI clock rates (6 MHz; 460kHz)
Removed TP11..14 muxes (CPLD space limitations)
Assigned TP11..14 to SDCARD SPI pins (easier debugging)
Bumped version #