Revert "ARM: cacheflush: add synchronization helpers for mixed cache state accesses"

This reverts commit aed2f0721a23c88077c27b8dc4dcda67382643b0.
Revert "ARM: suspend: use hash of cpu_logical_map value to index into save array"

This reverts commit 831327fa2942b6f48c42bd3bd60048f8fcfb9f19.
Revert "ARM: kernel: implement stack pointer save array through MPIDR hashing"

This reverts commit 1607c967cb69b6eb63d564c6bbd5518cde743d21.
Revert "ARM: kernel: build MPIDR hash function data structure"

This reverts commit d8a0222db480df269ddabe6f1aa681fdedceb176.
ARM: cacheflush: add synchronization helpers for mixed cache state accesses

Algorithms used by the MCPM layer rely on state variables which are
accessed while the cache is either active or inactive, depending
on the code path and the active state.

This patch introduces generic cache maintenance helpers to provide the
necessary cache synchronization for such state variables to always hit
main memory in an ordered way.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>