Clean up redundant comments
Update README.md

Added register to the list of modules to be created
Create isa_spec.md

Initial commit of the instruction set spec.
Add git ignore for GHDL output
First attempt at adding assertions to testbench
Merge pull request #7 from willprice/feature/clean_code

Clean up redundant comments - agreement reached.
Merge branch 'master' of github.com:willprice/vhdl-computer
Updated git ignore to include .swp temp files
Added several simple modules that can be used to test the build system.

dd_dtype, ff_jk and both mux modules should compile and elaborate fine. reg_shift is
currently broken pending investigation.
 On branch dev_ben
 Changes to be committed:

	renamed:    src/rtl/mux.vhd -> mux_2to1.vhd
	new file:   src/rtl/ff_dtype.vhd
	new file:   src/rtl/ff_jk.vhd
	new file:   src/rtl/mux_4to1.vhd
	new file:   src/rtl/reg_shift.vhd
Removed accidental file
Merge pull request #12 from willprice/dev_ben

Merge dev_ben into develop