configure: add a configuration step, prepare for 64bit compilation

adjust some types to be able to compile successfully on 64 bit.
To make it cleanly, add a configure step to check for the
appropriate types to use.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
.gitignore: add generated files

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risu_reginfo_arm: new module for the reginfo struct

put the struct reginfo and its methods in a separate module.
This also addresses the problem with the memcmp
being used directly on the struct without the memset 0.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risu_aarch64: provide risu initial implementation for aarch64

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
risu_aarch64, risu_arm: do not add to NULL

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
risu_aarch64, risu_arm: do not use NULL in subtraction either.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
configure: add -h,--help text, also add CPPFLAGS

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risugen: adapt for aarch64

still float missing, test missing, yadda yadda.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Makefile: pass CFLAGS also to gcc when linking

Useful for sysroot situations.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64: fix signal handling

fix signal handling to work on aarch64.
We don't mess with SP, mainly.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risugen: comment fixes

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risu.c: add missing <string.h> include for memset

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: implement first instructions

implement instructions that do not set flags,
and do not use floating point / SIMD,
and do not use / modify PC.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risugen: implement memory block setup for aarch64

Eventually we will need to split the script into an
arch-independent part and an arch-dependent part
like the rest of the code.

Big thing to note is that this changes the length of the memory
block for loads and stores to the actual documented value of
~2K bytes of random data. Before, ~2K 32-bit words of random data
were written, for a total of ~8K. Not sure if this was intended,
but seems a bug, which gets fixed here.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: remove broken comment

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu, risugen: add some comments

non-functional change.
adds comments explaining problems, especially regarding load/stores.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add first memory instruction (STXRB)

our very first memory instruction. Seems to work for now.
Covering the whole range of addressing modes will be hard with
the existing risu ARM assumptions.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add store exclusive insns for 8/16bit stores.

add STLXRB, STLRB,
STXRH, STLXRH, STLRH.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add load exclusive insns for 8/16bit data

add LDXRB, LDAXRB, LDARB, LDXRH, LDAXRH, LDARH.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add load/store excl insns for 32/64bit data

add STXR, STLXR, STLR, LDXR, LDAXR, LDAR for 32bit and 64bit.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>