removed sunxi_iis.slave setting _dai_probe since it is set before in _dai_probe
fixed Master Clock: _set_sysctl sets now the correct PLL. Corrected in _set_clkdiv the values of the dividers MCLKDIV and BCLKDIV. In addition SUNXI_SAMPLING_FREQ now enables the Master Clock output and prevents to clear/reset MCLK and BCLK
fixed Word Size Setting in case of samp_res > ws_size