mfd: as3722: make FUSE7_REG readable

The FUSE7_REG register is not currently marked readable. This causes
as3722_sd0_is_low_voltage() to emit an error during boot, and assume
the range of the SD0 regulator:

as3722-regulator as3722-regulator: Reg 0xa7 read failed: -5

Fixes: d4807ad2c4c0 ("regmap: Check readable regs in _regmap_read")
[exposed the bug, by checking for readability]
Fixes: 762a8ee80897 ("regulator: as3722: detect SD0 low-voltage mode")
[left out this register from the readable list]
Cc: Mark Brown <broonie@linaro.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
Note: I believe the regmap commit mentioned above is for 3.15, whereas
the as3722 commit is in at least 3.14. So, this only needs to be applied
for 3.15, but might make sense to go into earlier kernels, at your
discretion.
ARM: tegra: use 2 address cells for Tegra124 DT

Tegra124 can support 4GB of RAM. With that much RAM (plus some memory-
mapped IO peripherals), more than 32-bits of physical address space is
required. Hence, convert all Tegra124 DTs to use 2 DT cells for address
space.

(I think this was suggested by Olof Johansson, but I'm not 100% sure)

Signed-off-by: Stephen Warren <swarren@nvidia.com>
genirq: define flag IRQ_SRC_DST_INVERTED, and accessors

Some devices have configurable IRQ output polarities. Software might
use IRQ_TYPE_* to determine how to configure such a device's IRQ
output polarity in order to match how the IRQ controller input is
configured. If the board or SoC inverts the signal between the
device's IRQ output and controller's IRQ output, software must be
aware of this fact, in order to program the IRQ output to the correct
(i.e. opposite) polarity. This flag provides that information.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3: New patch.
dt: define IRQ flags bit 4 as src/dst inversion

Some devices have configurable IRQ output polarities. Software might
use IRQ specifier flag bits[3:0] to determine how to configure such a
device's IRQ output polarity in order to match how the IRQ controller
input is configured. If the board or SoC inverts the signal between the
device's IRQ output and controller's IRQ output, software must be
aware of this fact, in order to program the IRQ output to the correct
(i.e. opposite) polarity. This flag provides that information.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3: New patch.
irqchip: gic: parse IRQ specifier flag src/dst inversion

Modify the GIC driver to parse IRQ specifier flag bit 4 (src/dst
inverted) in the xlate function.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3: New patch.
mfd: palmas: support IRQ inversion at the board level

Implement the new DT property ti,irq-externally-inverted, and add an
equivalent platform data field to match. This allows the driver to
correctly automatically configure the IRQ output polarity when the board
or SoC contains an inverter between the Palmas IRQ output and IRQ
controller input.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3:
* Use an IRQD flag to represent the data, rather than a custom DT property.
v2:
* Split V1's patch 1/2 into separate patches 1/3 and 2/3.
ARM: tegra: fix Dalmore PMIC IRQ polarity

The Tegra PMC's resume-from-sleep logic wants an active-low IRQ input
from the PMIC. However, the PMIC IRQ is also routed to the GIC, which
only supports active high IRQs (or rising edge). Hence, the signal must
be inverted in the PMC before being routed to the GIC. This implies that
the PMC DT property nvidia,invert-interrupt must be set, and it is.

The PMIC's DT interrupts property must represent the IRQ level at the
GIC, since that is the PMIC's parent IRQ controller. Fix the PMIC's
interrupts property to correctly describe the GIC input polarity.

However, the PMIC IRQ output's polarity is programmable in HW, and by
default follows the parent IRQ controller's input polarity. We need to
have an active-low output due to the inversion inside the Tegra PMC.
Hence, add the IRQ specifier flag which request that to the PMIC.

Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3: Update to match changes to IRQ specifier DT binding.
v2: No change.
ASoC: dmaengine: remove SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME

struct snd_dmaengine_pcm_config's new chan_names field implements the
same feature, and nothing uses SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME,
so remove it.

FIXME: Need to create a patch to ASoC's topic/samsung(?) branch to stop
it from using SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME first...

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ASoC: dmaengine: remove compat_request_channel

struct snd_dmaengine_pcm_config's compat_request_channel field is no
longer set anywhere. Remove it, and the code that implements it.

FIXME: Need to wait for ux500 driver not to be using this feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
LOCAL HACK: tegra_defconfig changes

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: bluetooth testing hacks for Cardhu

Signed-off-by: Stephen Warren <swarren@nvidia.com>
HACK: Attempt to get DMICs working
Revert "HACK: Attempt to get DMICs working"

This reverts commit 7696d3e61c2dd5ce3f480083dc506be340062a9b.
ASoC: wm8903: disable IRQs during BIAS_OFF

If the WM8903 IRQ is triggered after the device is suspended, or before
it is resumed, the underlying I2C bus that the WM8903 is attached to may
not be available. This may cause the IRQ handler to emit the following
error:

    wm8903 0-001a: Failed to read IRQ status: -16

... or perhaps even cause a failure inside the I2C driver.

To prevent this, explicitly mask all interrupt sources when entering
BIAS_OFF. Also, modify the IRQ handler to immediately return if the
device is in BIAS_OFF, so that shared interrupt lines don't cause a
similar problem. This requires that WM8903 interrupts be disabled to
avoid interrupt storms.

During resume (actually, the transition back to BIAS_STANDBY), restore
the desired IRQ mask.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Revert "ASoC: wm8903: disable IRQs during BIAS_OFF"

This reverts commit 294680591cf91d99c1af375c055d39813338a04c.
HACK: attempt to convert sound/soc/samsung for ASoC DMA changes
Revert "HACK: attempt to convert sound/soc/samsung for ASoC DMA changes"

This reverts commit e072db5ec5c3f957196e602cd414e1518ee8a966.
HACK venice2 not to use an audio CODEC
HACK venice2 to work on tegrasim again
Revert "HACK venice2 to work on tegrasim again"

This reverts commit ca881fab84612917149afb3ace3601f7ceeaa8ef.