x86: Mark internal svm.c variables static

Some of the variables designed for internal use in svm.c were missing
a 'static' qualifier originally.
x86: Make ASID values local to CPU

Previously, Jailhouse forced ASID values to be unique across
all CPUs in the system. This sharing is somewhat problematic
(in recent AMD processors, there are few ASIDs available) and
useless in our scenario, since we don't migrate guests between
CPUs. This means, only host (ASID 0) or guest (ASID 1) can run
at each given CPU.
x86: Flush TLB on some AMD-V guest state changes

Some changes made to guest's VMCB requires hypervisor to flush guest's
TLB in software, which was not done previously. This commit fixes it,
however it is assumed that the guest never changes EFER.LMA directly.
x86: Remap SVM parking code at 0xffff0

Previously, Jailhouse was mapping CPU parking code at 0xfffff000
(aka x86 reset vector). To be consistent with the rest of the codebase
(and save a few lines of code), it is now remapped at 0xffff0 (aka
Jailhouse reset vector).
x86: Make use of VMCB clean bits

After a cell is created, Jailhouse doesn't change its VMCB much.
This means VMCB Clean Bits (APMv2, Sect. 15.15.1) have a good
potential to reduce world switch times.

This commit introduces VMCB Clean Bits support in Jailhouse. On each
VM exit, VMCB is marked as clean (unmodified), and each function that
changes guest state in VMCB is responsible for clearing the bit.

This is an optional feature, however it is cheap and harmless even
on CPUs that don't support it. That's said, VMCB Clean Bits are
now unsupported even on Kabini chips.
x86: Flush TLB when parking an AMD-V vcpu

AMD-V parking code doesn't reference memory; however it is better to
flush TLB with nested CR3 change.
x86: Implement SVM state tracking

Compared to VMX, there is no hard need for state tracking in AMD-V
code. For now, we implement 'on' and 'off' states and refuse to switch
SVM off for CPUs we haven't switched it on before.
x86: Introduce realmode_paging structures

Real mode certainly has no paging, but having these structures
unifies guest memory access. AMD-V code may need to read guest
instructions even for cells running in real mode.
x86: Simplify x86_parse_mov_to_cr()

Make use of realmode_paging structures available now to cut off
some branching.
x86: Fix operand qualifier in vcpu_activate_vmm()

Actually, nothing prevents us from using (m) for vmcb_pa.
x86: Switchable guest code access for mmio_parse()

Refactored mmio_parse() and related to use link-time resolved, rather
than hardcoded static function, to access guest memory. This way,
vendor-specific code can provide accelerated implementations if needed.

Code access function usage was also changed: it now returns pointer to the
first byte available and accepts the number of bytes to map (or otherwise
make available for the hypervisor). The function can adjust this value (it is
now done to save an unnecessary page table walk), as described in <asm/vcpu.h>.
x86: Updated guest code access in AMD-V code

Make use of recent changes to mmio_parse() infrastrcture in AMD-V:
provide accelerated implementation for vcpu_get_inst_bytes(), and
use stock vcpu_map_inst() instead of the custom static function
in x86_parse_mov_to_cr().
x86: Add warning message for AMD IOMMU

AMD IOMMU support is not implemented yet, so we warn Jailhouse users
it's unavailable.