iommu/arm-smmu: Play nice on non-ARM/SMMU systems

Currently the driver registers IOMMU bus operations for all busses even
if no ARM SMMU is present on a system. Depending on the driver probing
order this prevents the driver for the real IOMMU to register itself as
the bus-wide IOMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Implement memory-controller clock

The memory controller clock runs either at half or the same frequency as
the EMC clock.

Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v4:
- use name and parent name parameters passed in when registering clock

Changes in v3:
- split registration into a separate function that can be reused for all
  SoC generations, but pass in the name and parent parameters for
  clarity as well as the register address (in case it ever changes) and
  the EMC spin-lock since it isn't globally available
amba: Add Kconfig file

Rather than duplicate the ARM_AMBA Kconfig symbol in both 32-bit and
64-bit ARM architectures, move the common definition to drivers/amba
where dependent drivers will be located.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Move AHB Kconfig to drivers/amba

This will allow the Kconfig option to be shared among 32-bit and 64-bit
ARM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v4:
- add precursory patch introducing drivers/amba/Kconfig, rebase on top

Changes in v3:
- select ARM_AMBA from ARCH_TEGRA to enable the TEGRA_AHB driver
of: Add NVIDIA Tegra memory controller binding

The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.

In addition, the memory controller implements an SMMU (IOMMU) which can
translate I/O virtual addresses to physical addresses for clients. This
is useful for scatter-gather operation on devices that don't support it
natively and for virtualization or process separation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- add missing clocks and clock-names properties
- add example
memory: Add NVIDIA Tegra memory controller support

The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.

Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this driver (via a
custom API or a generic subsystem) to allow clients to register latency
requirements.

This driver also registers an IOMMU (SMMU) that's implemented by the
memory controller. It is supported on Tegra30, Tegra114 and Tegra124
currently. Tegra20 has a GART instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v6:
- add Kconfig options so that dependencies can be properly encoded
- split memory-controller and SMMU code into separate files
- move num_address_bits field from SMMU to MC structure

Changes in v5:
- remove unused tegra_mc_set_bandwidth() function
- split Tegra132 support into a separate patch
- use correct register for GPU SWGROUP
- fix build failures on 64-bit

Changes in v4:
- remove DMA/IOMMU integration glue
- don't initialize linear SMMU mapping
- fail attachment for non-masters
- free empty page tables

Changes in v3:
- drop changes related to probe ordering that were rejected
- remove old SMMU driver
ARM: tegra: Add memory controller support for Tegra30

Collapses the old memory-controller and IOMMU device tree nodes into a
single node to more accurately describe the hardware.

While this is an incompatible change there are no users of the IOMMU on
Tegra, even though a driver has existed for some time.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Add memory controller support for Tegra114

Add the device tree node for the memory controller found on Tegra114
SoCs. The memory controller integrates an IOMMU (called SMMU) as well as
various knobs to tweak memory accesses by the various clients.

The old IOMMU device tree node is collapsed into the memory controller
node to more accurately describe the hardware. While this change is
incompatible, the IOMMU driver has never had any users so the change is
not going to cause any breakage.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Add memory controller support for Tegra124

Add the memory controller and wire up the interrupt that is used to
report errors. Provide a reference to the memory controller clock and
mark the device as being an IOMMU by adding an #iommu-cells property.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Enable IOMMU for display controllers on Tegra30

Add iommus properties to the device tree nodes for the two display
controllers found on Tegra30. This will allow the display controllers to
map physically non-contiguous buffers to I/O virtual contiguous address
spaces so that they can be used for scan-out.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Enable IOMMU for display controllers on Tegra114

Add iommus properties to the device tree nodes for the two display
controllers found on Tegra114. This will allow the display controllers
to map physically non-contiguous buffers to I/O virtual contiguous
address spaces so that they can be used for scan-out.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Enable IOMMU for display controllers on Tegra124

Add iommus properties to the device tree nodes for the two display
controllers found on Tegra124. This will allow the display controllers
to map physically non-contiguous buffers to I/O virtual contiguous
address spaces so that they can be used for scan-out.

Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra132 support

The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Select ARM_DMA_USE_IOMMU

This enables IOMMU interoperation with the DMA mapping API so that
clients that use the DMA mapping API can seemlessly make use of an
existing IOMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Add IOMMU support

When an IOMMU device is available on the platform bus, allocate an IOMMU
domain and attach the display controllers to it. The display controllers
can then scan out non-contiguous buffers by mapping them through the
IOMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v4:
- error out if IOMMU attachment fails

Changes in v3:
- create write-combined mappings for mmap()
- keep non-IOMMU fallback path working
- no longer rely on iommu_attach()

Changes in v2:
- don't pass GFP_KERNEL to drm_gem_get_pages()
drm/tegra: Use dma_mmap_writecombine()

Use the existing API rather than open-coding equivalent functionality
in the driver.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Add nouveau to Tegra config file
ARM: tegra: enable DRM staging option
ARM: tegra: venice2: add GK20A GPU DT node

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsability of the bootloader to enable it if the
VPR registers have been programmed such as the GPU can operate.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
ARM: tegra: jetson-tk1: add GK20A GPU DT node

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsability of the bootloader to enable it if the
VPR registers have been programmed such as the GPU can operate.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>