coredevice/runtime_exceptions: update RTIO exception behaviour doc
rtio: stricter upper bound on guard time to avoid race condition
rtio: optimize flag handling
frontend: rename files to avoid conflicts
frontend/runelf: use new Comm
targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
rtio: do housekeeping in gateware
rtio: remove unnecessary attributes
targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG
lda: allow to simulate without needing hidapi

This also fixes some old style string formating
manual: use theme options which looks like m-labs web site
comm_serial: allow to use dynamic baudrate
comm_serial: cleanup
runtime: support clock switching
coredevice/core: fix recover_underflow
transforms/inline: do not writeback bool
coredevice/comm_serial: give up on garbage received after baudrate change
language: replace AutoContext 'parameter' string with abstract attributes

This allows specifying default values for parameters, and other data.
add requirements.txt
add .travis.yml