added tested timing generator module

added TIME1 output for 48 msec TE interrupt for microprocessor
added tested timing generator module

added TIME1 port
added tested timing generator module

added modules related to timing generator
added tested timing generator module

added all modules related to timing generator
add cvs tracking macro
change timing gen signal from one_PPS_PIC_adv_tp to one_PPS_PIC_adv
fix assignment of Grs to data_interface (was on wrong bit)
add signal nchan to timing gen interface
add register 12 mappings for nchan and epoch
use c167 registers 5 to 8 to read out SFRE for test purposes
make C167 registers 3b to 3f readable
make C167 register 4 writeable for test purposes
slight differences in test point mappings
added tested timing generator module

added TIME1 output for 48 msec TE interrupt for microprocessor