Fixed timing issues with fetch and decode

I fixed it so that when the stall goes low the instruction is fetched in
one cycle and retrieved from memory. The instruction data is then ready
at the beginning of the next clock cycle (decode).
Timing is fixed. Writes to reg file not working

Got the timing sorted out so that we only execute one instruction at a
time and then the next one happens after the last one writes back. The
problem now is that the writes are not working to the reg file.