[include][sys] add shorthand integer types

u8/u16/u32/u64 and s8/s16/s32/s64 for those who prefer minimum verbosity
[platform][zynq] initial fpga control routines

- zynq_program_fpga(physaddr,len) -- load bitstream
- zynq_reset_fpga() -- reset fpga
[lib][devicetree] first pass at library for dealing with devicetree

Basic validation and walking of flattened devicetree blobs.
[platform][zynq] initial implementation of some clock routines

-Mostly introspection at this point
-Move target specific jam table to early platform init
[platform][zynq] update clock routines to lock/unlock
[platform][zynq] during init, write to mandatory reserved register
[target][zynq-qemu] get the qemu target working after clock changes

The qemu target seems to emulate a 33Mhz crystal with default
pll settings.