add a first version of the stub_fifo (untested)
implement fifo_fsm (untested)
add sc_delay_signal
the sc_delay_signal delays a signal by a number of clock cycles. The
class and its test bench are added.
adds AM board (not running - backup)
Merge commit '0daee18683fbe499d8c7f4301b99068069577959' into add_AM_chip
edit AM_board (backup commit - not running)
add some port naming that was missing
add am_board_tb (backup commit not running)
Merge commit '026526dd0fcd0172b2d929db842d8f73a6369656' into add_AM_chip
Update de sc_delay module
backup commit
add AM chip and AM ctrl (first running version)
add stub_fifo to main test bench
add AM controller to the main test bench