Merge pull request #1 from othane/master

update to intelhex 1.5
handle spi master addressing properly

this basically makes the old nss line an array of address/nss lines and
implements actual addressing in the spim_xfer() call and its callback
rather than just assuming the target is always selected by dropping only
one nss line

so basically now the nss in the spim object is a null terminated array
of gpio lines that work as either:
	* a array of nss lines or
	* a active lo bus (so if addressing 0x02 all gpio lines would be
	hi except for the second which would be hi)
these to modes are only conceptually different in that when an array of
nss lines is used the addresses would be 0x1, 0x2, 0x4, 0x8 etc but if a
proper bus is used then all values can be used ie 0x1, 0x2, 0x3, 0x4,
0x5... (it is important to note to make these modes the same the bus is
active lo).

so as an example usage if there was only one nss line like the old setup
the spim.nss = {&gpio_nss_line, NULL} ... however to support a 3 bit bus
(addressing up to 8 devices) you could do this spim.nss = {gpio_bus_b0,
gpio_bus_b1, gpio_bus_b2, NULL} ... note the first pin is the LSB, ie
bit 0
Merge pull request #5 from coherentsolutions/master

handle spi addressing properly