[mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6

Summary: Depends on D3957

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210775 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6

Summary:
c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to
dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's
(like the GPR comparisons).

mov[fntz] have been replaced by seleqz and selnez. These instructions
conditionally zero a register based on a bool in a GPR. The results can
then be or'd together to act as a select without, for example, requiring a third
register read port.

mov[fntz].[ds] have been replaced with sel.[ds]

MIPS64r6 currently generates unnecessary sign-extensions for most selects.
This is because the result of a SETCC is currently an i32. Bits 32-63 are
undefined in i32 and the behaviour of seleqz/selnez would otherwise depend
on undefined bits. Later, we will fix this by making the result of SETCC an
i64 on MIPS64 targets.

Depends on D3958

Reviewers: jkolek, vmedic, zoran.jovanovic

Reviewed By: vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D4003

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210777 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] 80 col corrections that should have been in r210777.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210778 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6

Summary: We haven't implemented this instruction so we only add a test case.

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D4004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210779 91177308-0d34-0410-b5e6-96231b3b80d8