armv7: provide compiler options for rmodules

In order to build rmodules for armv7 boards, the default
compiler options need to be set so the assembler sources
can correclty compile. For now assume rmodules for arm
devices use the ramstage compiler options.

BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built vboot as rmodule for nyan.

Original-Change-Id: I8d12a2a57944b187cbdff2f22176de5b4de87a54
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190926
(cherry picked from commit cd091ae8ced30e6e2543f36bdb5c14518e7879c3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I24706f7d72a53f71abd2770f0d12de8c6ed31f63
Reviewed-on: http://review.coreboot.org/7744
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
arm: Fix minor mistake in cache maintenance assembly

Turns out that when you clear 28 bits starting with bit 3, you leave bit
31 standing. Ooops...

This shouldn't really matter since that bit is reserved/SBZ in CLIDR
anyway, but it's still nice to fix it. This whole thing should really be
an AND for clarity anyway in my opinion.

Bug found in upstream NetBSD (who would've thought...).

BUG=None
TEST=Still boots.

Change-Id: Ic826e82d58fd1ce984971afea3dfa9296f746d9f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193300
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit d270c0ec18b74b272451c456cbf07e99d95896cb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7745
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
arm: Add support for a preram_cbmem_console symbol.

This symbol is set using a config variable which can be set to something
appropriate by the SOC. If it isn't, the symbol is set to 0 which should be
caught by checks in the cbmem console itself.

BUG=None
TEST=Built for nyan with a cbmem buffer location set. Built for peach_pit
without a location set.
BRANCH=None

Original-Change-Id: I92cd65bb6767a67637faf1dd3cdbe03e433724a9
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193165
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4f38c073bfe469a753e168391787fdd7bc5c34d9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I979037fe8cda885cc516d79f3151ca1fc77adca3
Reviewed-on: http://review.coreboot.org/7746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
elog: Probe for SPI flash on bus indicated by Kconfig variable

This replaces a hard-coded bus number of 0 with a Kconfig variable,
CONFIG_BOOT_MEDIA_SPI_BUS. This removes an assumption made for x86
where this value is always 0 and makes it easy to add support for
other platforms where the bus number for the backing SPI flash is
more arbitrary.

BUG=none
BRANCH=none
TEST=tested on Nyan (bus=4) and Link (bus=0)
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I1e878a1628af7f4ccc2f39a70b2190192767e536
Original-Reviewed-on: https://chromium-review.googlesource.com/194854
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 371c6c14d8d4b98004eebce7049a88a219682bc4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie105b4654e028098f2137c96e4309b8d85f096df
Reviewed-on: http://review.coreboot.org/7753
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
x86: Set BOOT_MEDIA_SPI_BUS

BOOT_MEDIA_SPI_BUS is a Kconfig variable used on some ARM-based
platforms to set up CBFS media. It turns out it can also be helpful
for setting up the eventlog which is intended to reside on the same
SPI flash as CBFS. Setting it for x86 will allow us to remove an
assumption about which SPI bus is used for this flash device.

Long term this can go away as we come up with a better abstraction
for the eventlog's backing store. This is only intended to help us
get from here to there.

BUG=none
BRANCH=none
TEST=built and booted on Link
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I1d84dc28592fbece33a70167be59e83bca9cd7bc
Original-Reviewed-on: https://chromium-review.googlesource.com/191202
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 200aa7c5b1b1f4c74412893cf7231a12e2702463)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If988bcff5244ec6a82580203471b25fac49c45ef
Reviewed-on: http://review.coreboot.org/7752
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
i2c: Replace the i2c API.

The new API is in use in depthcharge and is based around the "i2c_transfer"
function instead of i2c_read and i2c_write. The new function takes an array of
i2c_seg structures which represent each portion of the transfer after a start
bit and before the stop bit. If there's more than one segment, they're
seperated by repeated starts.

Some wrapper functions have also been added which make certain common
operations easy. These include reading or writing a byte from a register or
reading or writing a blob of raw data. The i2c device drivers generally use
these wrappers but can call the i2c_transfer function directly if the need
something different.

The tegra i2c driver was very similar to the one in depthcharge and was simple
to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and
replace the ones in coreboot. The Exynos 5420 driver was ported from the high
speed portion of the one in coreboot and was straightforward to port back. The
low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot
and were replaced with the depthcharge implementation.

BUG=None
TEST=Built and booted on nyan with and without EFS. Built and booted on, pit
and daisy.
BRANCH=None

Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193561
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe)

This cherry-pick required additional changes to the following:
src/cpu/allwinner/a10/twi.c
src/drivers/xpowers/axp209/axp209.c

Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7
Reviewed-on: http://review.coreboot.org/7751
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>