MAINTAINERS: Add entry for APM X-Gene SoC ethernet driver

This patch adds a MAINTAINERS entry for APM X-Gene SoC
ethernet driver.

Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: Ravi Patel <rapatel@apm.com>
Signed-off-by: Keyur Chudgar <kchudgar@apm.com>
Documentation: dts: Add bindings for APM X-Gene SoC ethernet driver

This patch adds documentation for APM X-Gene SoC ethernet DTS binding.

Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: Ravi Patel <rapatel@apm.com>
Signed-off-by: Keyur Chudgar <kchudgar@apm.com>
dts: Add bindings for APM X-Gene SoC ethernet driver

Backport of a patch from Mark Salter's fedorahosted tree.

Signed-off-by: Al Stone <ahs3@redhat.com>

Original patch was:

    From ed37aec460cc6c46670fa712fef277efc5a96714 Mon Sep 17 00:00:00 2001
    From: Iyappan Subramanian <isubramanian@apm.com>
    Date: Mon, 2 Jun 2014 12:39:13 -0700
    Subject: [PATCH 03/87] dts: Add bindings for APM X-Gene SoC ethernet driver

    This patch adds bindings for APM X-Gene SoC ethernet driver.

    Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
    Signed-off-by: Ravi Patel <rapatel@apm.com>
    Signed-off-by: Keyur Chudgar <kchudgar@apm.com>
    ---
     arch/arm64/boot/dts/apm-mustang.dts |  4 ++++
     arch/arm64/boot/dts/apm-storm.dtsi  | 30 +++++++++++++++++++++++++++---
     2 files changed, 31 insertions(+), 3 deletions(-)

    diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts
    index 1247ca1..e2fb1ef 100644
    --- a/arch/arm64/boot/dts/apm-mustang.dts
    +++ b/arch/arm64/boot/dts/apm-mustang.dts
    @@ -24,3 +24,7 @@
     		reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
     	};
     };
    +
    +&menet {
    +	status = "ok";
    +};
    diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
    index c5f0a47..bd7a614 100644
    --- a/arch/arm64/boot/dts/apm-storm.dtsi
    +++ b/arch/arm64/boot/dts/apm-storm.dtsi
    @@ -167,14 +167,13 @@
     				clock-output-names = "ethclk";
     			};

    -			eth8clk: eth8clk {
    +			menetclk: menetclk {
     				compatible = "apm,xgene-device-clock";
     				#clock-cells = <1>;
     				clocks = <&ethclk 0>;
    -				clock-names = "eth8clk";
     				reg = <0x0 0x1702C000 0x0 0x1000>;
     				reg-names = "csr-reg";
    -				clock-output-names = "eth8clk";
    +				clock-output-names = "menetclk";
     			};

     			sataphy1clk: sataphy1clk@1f21c000 {
    @@ -363,5 +362,30 @@
     			#clock-cells = <1>;
     			clocks = <&rtcclk 0>;
     		};
    +
    +		menet: ethernet@17020000 {
    +			compatible = "apm,xgene-enet";
    +			status = "disabled";
    +			reg = <0x0 0x17020000 0x0 0xd100>,
    +			      <0x0 0X17030000 0x0 0X400>,
    +			      <0x0 0X10000000 0x0 0X200>;
    +			reg-names = "enet_csr", "ring_csr", "ring_cmd";
    +			interrupts = <0x0 0x3c 0x4>;
    +			dma-coherent;
    +			clocks = <&menetclk 0>;
    +			local-mac-address = [00 01 73 00 00 01];
    +			phy-connection-type = "rgmii";
    +			phy-handle = <&menetphy>;
    +			mdio {
    +				compatible = "apm,xgene-mdio";
    +				#address-cells = <1>;
    +				#size-cells = <0>;
    +				menetphy: menetphy@3 {
    +					compatible = "ethernet-phy-id001c.c915";
    +					reg = <0x3>;
    +				};
    +
    +			};
    +		};
     	};
     };
    --
    1.9.3
drivers: net: Add APM X-Gene SoC ethernet driver support.

This patch adds network driver for APM X-Gene SoC ethernet.

Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: Ravi Patel <rapatel@apm.com>
Signed-off-by: Keyur Chudgar <kchudgar@apm.com>
libahci: Implement the function ahci_restart_engine to restart the port dma engine.

Backport of patch from Mark Salter's fedorahosted tree.

Signed-off-by: Al Stone <ahs3@redhat.com>

Original patch:

    From d26272ba9aaeed312173d8d3625f55889d9d2f4d Mon Sep 17 00:00:00 2001
    From: Suman Tripathi <stripathi@apm.com>
    Date: Thu, 12 Jun 2014 12:11:21 -0400
    Subject: [PATCH 05/87] libahci: Implement the function ahci_restart_engine to
     restart the port dma engine.

    This patch implements the function ahci_restart_engine function to
    restart the port dma engine.

    Signed-off-by: Loc Ho <lho@apm.com>
    Signed-off-by: Suman Tripathi <stripathi@apm.com>
    ---
     drivers/ata/ahci.h    |  1 +
     drivers/ata/libahci.c | 10 ++++++++++
     2 files changed, 11 insertions(+)

    diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
    index 05882e4..14328d1 100644
    --- a/drivers/ata/ahci.h
    +++ b/drivers/ata/ahci.h
    @@ -373,6 +373,7 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,

     int ahci_stop_engine(struct ata_port *ap);
     void ahci_start_engine(struct ata_port *ap);
    +int ahci_restart_engine(struct ata_port *ap);
     int ahci_check_ready(struct ata_link *link);
     int ahci_kick_engine(struct ata_port *ap);
     int ahci_port_resume(struct ata_port *ap);
    diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
    index 40ea583..4234bab 100644
    --- a/drivers/ata/libahci.c
    +++ b/drivers/ata/libahci.c
    @@ -747,6 +747,16 @@ static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
     	return 0;
     }

    +int ahci_restart_engine(struct ata_port *ap)
    +{
    +	ahci_stop_engine(ap);
    +	ahci_start_fis_rx(ap);
    +	ahci_start_engine(ap);
    +
    +	return 0;
    +}
    +EXPORT_SYMBOL_GPL(ahci_restart_engine);
    +
     #ifdef CONFIG_PM
     static void ahci_power_down(struct ata_port *ap)
     {
    --
    1.9.3
ata: Fix the dma state machine lockup for the PIO mode commands.

Backport of patch from Mark Salter's fedorahosted tree.

Signed-off-by: Al Stone <ahs3@redhat.com>

Original patch:

    From 0256ca8f03e833c420e45d03a396add0d7cef695 Mon Sep 17 00:00:00 2001
    From: Suman Tripathi <stripathi@apm.com>
    Date: Thu, 12 Jun 2014 12:11:22 -0400
    Subject: [PATCH 06/87] ata: Fix the dma state machine lockup for the PIO mode
     commands.

    This patch fixes the dma state machine lockup due to the PIO mode
    commands. The controller is unable to clear the BSY bit after
    receiving the PIO setup FIS and results the dma state machine
    to go into the CMFataErrorUpdate state resulting in dma
    state machine lockup.

    Signed-off-by: Loc Ho <lho@apm.com>
    Signed-off-by: Suman Tripathi <stripathi@apm.com>
    [forward ported]
    Signed-off-by: Mark Salter <msalter@redhat.com>
    ---
     drivers/ata/ahci.h       |  2 ++
     drivers/ata/ahci_xgene.c | 17 +++--------------
     drivers/ata/libahci.c    | 33 +++++++++++++++++++++++++++++++++
     3 files changed, 38 insertions(+), 14 deletions(-)

    diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
    index 14328d1..b72d0a3 100644
    --- a/drivers/ata/ahci.h
    +++ b/drivers/ata/ahci.h
    @@ -238,6 +238,8 @@ enum {
     	AHCI_HFLAG_MULTI_MSI		= (1 << 16), /* multiple PCI MSIs */
     	AHCI_HFLAG_NO_DEVSLP		= (1 << 17), /* no device sleep */
     	AHCI_HFLAG_NO_FBS		= (1 << 18), /* no FBS */
    +	AHCI_HFLAG_BROKEN_PIO_CMD	= (1 << 19), /* PIO cmds resulting in
    +							HBA dma state lockup */

     	/* ap->flags bits */

    diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
    index 042a9bb..ebbc4d88 100644
    --- a/drivers/ata/ahci_xgene.c
    +++ b/drivers/ata/ahci_xgene.c
    @@ -104,14 +104,12 @@ static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
      * @id: data buffer
      *
      * This custom read ID function is required due to the fact that the HW
    - * does not support DEVSLP and the controller state machine may get stuck
    - * after processing the ID query command.
    + * does not support DEVSLP.
      */
     static unsigned int xgene_ahci_read_id(struct ata_device *dev,
     				       struct ata_taskfile *tf, u16 *id)
     {
     	u32 err_mask;
    -	void __iomem *port_mmio = ahci_port_base(dev->link->ap);

     	err_mask = ata_do_dev_read_id(dev, tf, id);
     	if (err_mask)
    @@ -133,16 +131,6 @@ static unsigned int xgene_ahci_read_id(struct ata_device *dev,
     	 */
     	id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8);

    -	/*
    -	 * Due to HW errata, restart the port if no other command active.
    -	 * Otherwise the controller may get stuck.
    -	 */
    -	if (!readl(port_mmio + PORT_CMD_ISSUE)) {
    -		writel(PORT_CMD_FIS_RX, port_mmio + PORT_CMD);
    -		readl(port_mmio + PORT_CMD);	/* Force a barrier */
    -		writel(PORT_CMD_FIS_RX | PORT_CMD_START, port_mmio + PORT_CMD);
    -		readl(port_mmio + PORT_CMD);	/* Force a barrier */
    -	}
     	return 0;
     }

    @@ -450,7 +438,8 @@ static int xgene_ahci_probe(struct platform_device *pdev)
     		goto disable_resources;
     	}

    -	hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
    +	hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ |
    +		 AHCI_HFLAG_BROKEN_PIO_CMD;

     	rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info,
     				     hflags, 0, 0);
    diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
    index 4234bab..a56ba75 100644
    --- a/drivers/ata/libahci.c
    +++ b/drivers/ata/libahci.c
    @@ -1597,6 +1597,31 @@ static void ahci_fbs_dec_intr(struct ata_port *ap)
     		dev_err(ap->host->dev, "failed to clear device error\n");
     }

    +int ahci_complete_pio_cmd(struct ata_port *ap, u32 cmd_done)
    +{
    +	struct ata_queued_cmd *qc;
    +
    +	while (cmd_done) {
    +		unsigned int tag = __ffs(cmd_done);
    +
    +		qc = ata_qc_from_tag(ap, tag);
    +		if (qc) {
    +			/*
    +			 * Some controller unable to clear the BSY bit after
    +			 * receiving the PIO Setup FIS from device resulting
    +			 * the DMA state to go into CMFatalErrorUpdate state.
    +			 * So need to restart the dma engine to get the
    +			 * controller out of this state.
    +			 */
    +			if (qc->tf.protocol == ATA_PROT_PIO)
    +				ahci_restart_engine(ap);
    +		}
    +		cmd_done &= ~(1 << tag);
    +	}
    +
    +	return 0;
    +}
    +
     static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
     {
     	struct ahci_host_priv *hpriv = ap->host->private_data;
    @@ -1783,6 +1808,14 @@ static void ahci_handle_port_interrupt(struct ata_port *ap,
     	}

    +	/* Due to HW errata, some controllers need special handling
    +	 * of the completion of the PIO commands.
    +	 */
    +       	if (hpriv->flags & AHCI_HFLAG_BROKEN_PIO_CMD) {
    +		u32 cmd_done = ap->qc_active ^ qc_active;
    +		ahci_complete_pio_cmd(ap, cmd_done);
    +	}
    +
     	rc = ata_qc_complete_multiple(ap, qc_active);

     	/* while resetting, invalid completions are expected */
    --
    1.9.3
arm64: fix MAX_ORDER for 64K pagesize

With a kernel configured with ARM64_64K_PAGES && !TRANSPARENT_HUGEPAGE
I get this at early boot:

  SMP: Total of 8 processors activated.
  devtmpfs: initialized
  Unable to handle kernel NULL pointer dereference at virtual address 00000008
  pgd = fffffe0000050000
  [00000008] *pgd=00000043fba00003, *pmd=00000043fba00003, *pte=00e0000078010407
  Internal error: Oops: 96000006 [#1] SMP
  Modules linked in:
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.15.0-rc864k+ #44
  task: fffffe03bc040000 ti: fffffe03bc080000 task.ti: fffffe03bc080000
  PC is at __list_add+0x10/0xd4
  LR is at free_one_page+0x270/0x638
  ...
  Call trace:
  [<fffffe00003ee970>] __list_add+0x10/0xd4
  [<fffffe000019c478>] free_one_page+0x26c/0x638
  [<fffffe000019c8c8>] __free_pages_ok.part.52+0x84/0xbc
  [<fffffe000019d5e8>] __free_pages+0x74/0xbc
  [<fffffe0000c01350>] init_cma_reserved_pageblock+0xe8/0x104
  [<fffffe0000c24de0>] cma_init_reserved_areas+0x190/0x1e4
  [<fffffe0000090418>] do_one_initcall+0xc4/0x154
  [<fffffe0000bf0a50>] kernel_init_freeable+0x204/0x2a8
  [<fffffe00007520a0>] kernel_init+0xc/0xd4

This happens in this configuration because __free_one_page() is called
with an order greater than MAX_ORDER, accesses past zone->free_list[]
and passes a bogus list_head to list_add().

arch/arm64/Kconfig has:

  config FORCE_MAX_ZONEORDER
	int
	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
	default "11"

So with THP turned off MAX_ORDER == 11 but init_cma_reserved_pageblock()
passes __free_pages() an order of pageblock_order which is based on
(HPAGE_SHIFT - PAGE_SHIFT) which is 13 for 64K pages. I worked around
this by removing the THP test so FORCE_MAX_ZONEORDER is always 14 for
ARM64_64K_PAGES.

Signed-off-by: Mark Salter <msalter@redhat.com>
arm64: fix soft lockup due to large tlb flush range

Under certain loads, this soft lockup has been observed:

   BUG: soft lockup - CPU#2 stuck for 22s! [ip6tables:1016]
   Modules linked in: ip6t_rpfilter ip6t_REJECT cfg80211 rfkill xt_conntrack ebtable_nat ebtable_broute bridge stp llc ebtable_filter ebtables ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_security ip6table_raw ip6table_filter ip6_tables iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack iptable_mangle iptable_security iptable_raw vfat fat efivarfs xfs libcrc32c

   CPU: 2 PID: 1016 Comm: ip6tables Not tainted 3.13.0-0.rc7.30.sa2.aarch64 #1
   task: fffffe03e81d1400 ti: fffffe03f01f8000 task.ti: fffffe03f01f8000
   PC is at __cpu_flush_kern_tlb_range+0xc/0x40
   LR is at __purge_vmap_area_lazy+0x28c/0x3ac
   pc : [<fffffe000009c5cc>] lr : [<fffffe0000182710>] pstate: 80000145
   sp : fffffe03f01fbb70
   x29: fffffe03f01fbb70 x28: fffffe03f01f8000
   x27: fffffe0000b19000 x26: 00000000000000d0
   x25: 000000000000001c x24: fffffe03f01fbc50
   x23: fffffe03f01fbc58 x22: fffffe03f01fbc10
   x21: fffffe0000b2a3f8 x20: 0000000000000802
   x19: fffffe0000b2a3c8 x18: 000003fffdf52710
   x17: 000003ff9d8bb910 x16: fffffe000050fbfc
   x15: 0000000000005735 x14: 000003ff9d7e1a5c
   x13: 0000000000000000 x12: 000003ff9d7e1a5c
   x11: 0000000000000007 x10: fffffe0000c09af0
   x9 : fffffe0000ad1000 x8 : 000000000000005c
   x7 : fffffe03e8624000 x6 : 0000000000000000
   x5 : 0000000000000000 x4 : 0000000000000000
   x3 : fffffe0000c09cc8 x2 : 0000000000000000
   x1 : 000fffffdfffca80 x0 : 000fffffcd742150

The __cpu_flush_kern_tlb_range() function looks like:

  ENTRY(__cpu_flush_kern_tlb_range)
	dsb	sy
	lsr	x0, x0, #12
	lsr	x1, x1, #12
  1:	tlbi	vaae1is, x0
	add	x0, x0, #1
	cmp	x0, x1
	b.lo	1b
	dsb	sy
	isb
	ret
  ENDPROC(__cpu_flush_kern_tlb_range)

The above soft lockup shows the PC at tlbi insn with:

  x0 = 0x000fffffcd742150
  x1 = 0x000fffffdfffca80

So __cpu_flush_kern_tlb_range has 0x128ba930 tlbi flushes left
after it has already been looping for 23 seconds!.

Looking up one frame at __purge_vmap_area_lazy(), there is:

	...
	list_for_each_entry_rcu(va, &vmap_area_list, list) {
		if (va->flags & VM_LAZY_FREE) {
			if (va->va_start < *start)
				*start = va->va_start;
			if (va->va_end > *end)
				*end = va->va_end;
			nr += (va->va_end - va->va_start) >> PAGE_SHIFT;
			list_add_tail(&va->purge_list, &valist);
			va->flags |= VM_LAZY_FREEING;
			va->flags &= ~VM_LAZY_FREE;
		}
	}
	...
	if (nr || force_flush)
		flush_tlb_kernel_range(*start, *end);

So if two areas are being freed, the range passed to
flush_tlb_kernel_range() may be as large as the vmalloc
space. For arm64, this is ~240GB for 4k pagesize and ~2TB
for 64kpage size.

This patch works around this problem by adding a loop limit.
If the range is larger than the limit, use flush_tlb_all()
rather than flushing based on individual pages. The limit
chosen is arbitrary and would be better if based on the
actual size of the tlb. I looked through the ARM ARM but
didn't see any easy way to get the actual tlb size, so for
now the arbitrary limit is better than the soft lockup.

Signed-off-by: Mark Salter <msalter@redhat.com>
arm64: support reboot and power off via EFI runtime

Add handlers for arm_pm_resestart and pm_power_off which use EFI
runtime services ResetSystem call to perform the functions. These
handlers are only installed if no handler currently exists. This
allows PSCI to take priority over EFI for these functions.

Signed-off-by: Mark Salter <msalter@redhat.com>
arm64: don't set READ_IMPLIES_EXEC for EM_AARCH64 ELF objects

Message-id: <20140513222526.GC26038@redacted.bos.redhat.com>
Patchwork-id: 79789
O-Subject: [ACADIA PATCH] arm64: don't set READ_IMPLIES_EXEC for EM_AARCH64 ELF objects
Bugzilla: 1085528

BZ: https://bugzilla.redhat.com/show_bug.cgi?id=1085528
Upstream: submitted soon

[Sadly this isn't (yet) sufficient... but it fixes at least one issue
 here... cat /proc/$$/personality shows READ_IMPLIES_EXEC before. I'll
 try to figure the rest out tomorrow.]

Currently, we're accidentally ending up with executable stacks on
AArch64 when the ABI says we shouldn't be, and relying on glibc to fix
things up for us when we're loaded. However, SELinux will deny us
mucking with the stack, and hit us with execmem AVCs.

The reason this is happening is somewhat complex:

fs/binfmt_elf.c:load_elf_binary()
 - initializes executable_stack = EXSTACK_DEFAULT implying the
   architecture should make up its mind.
 - does a pile of loading goo
 - runs through the program headers, looking for PT_GNU_STACK
   and setting (or unsetting) executable_stack if it finds it.

   This is our first problem, we won't generate these unless an
   executable stack is explicitly requested.

 - more ELF loading goo
 - sets whether we're a compat task or not (TIF_32BIT) based on compat.h
 - for compat reasons (pre-GNU_STACK) checks if the READ_IMPLIES_EXEC
   flag should be set for ancient toolchains

   Here's our second problem, we test if read_implies_exec based on
   stk != EXSTACK_DISABLE_X, which is true since stk == EXSTACK_DEFAULT.

   So we set current->personality |= READ_IMPLIES_EXEC like a broken
   legacy toolchain would want.

 - Now we call setup_arg_pages to set up the stack...

fs/exec.c:setup_arg_pages()
 - lots of magic happens here
 - vm_flags gets initialized to VM_STACK_FLAGS

   Here's our third problem, VM_STACK_FLAGS on arm64 is
   VM_DEFAULT_DATA_FLAG which tests READ_IMPLIES_EXEC and sets VM_EXEC
   if it's true. So we end up with an executable stack mapping, since we
   don't have executable_stack set (it's still EXSTACK_DEFAULT at this
   point) to unset it anywhere.

Bang. execstack AVC when the program starts running.

The easiest way I can see to fix this is to test if we're a legacy task
and fix it up there. But that's not as simple as it sounds, because
the 32-bit ABI depends on what revision of the CPU we've enabled (not
that it matters since we're ARMv8...) Regardless, in the compat case,
set READ_IMPLIES_EXEC if we've found a GNU_STACK header which explicitly
requested it as in arch/arm/kernel/elf.c:arm_elf_read_implies_exec().

Signed-off-by: Kyle McMartin <kmcmarti@redhat.com>
Signed-off-by: Donald Dutile <ddutile@redhat.com>
arm64: fix up APM Mustang devicetree

Backport of patch from Mark Salter's fedorahosted tree.

Signed-off-by: Al Stone <ahs3@redhat.com>

Original patch:

    From 481672c745785e2e4c3dac6defc419ff143bc46c Mon Sep 17 00:00:00 2001
    From: Mark Salter <msalter@redhat.com>
    Date: Sun, 15 Jun 2014 09:06:55 -0400
    Subject: [PATCH 12/87] arm64: fix up APM Mustang devicetree

    These are changes needed when loading device tree blob built with
    kernel. i.e. with grub. These are not needed when using devicetree
    from Tianocore which will be fixed up at tianocore runtime.

    Signed-off-by: Mark Salter <msalter@redhat.com>
    ---
     arch/arm64/boot/dts/apm-storm.dtsi | 20 ++++++++++----------
     1 file changed, 10 insertions(+), 10 deletions(-)

    diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
    index bd7a614..39fe51a 100644
    --- a/arch/arm64/boot/dts/apm-storm.dtsi
    +++ b/arch/arm64/boot/dts/apm-storm.dtsi
    @@ -24,56 +24,56 @@
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x000>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     		cpu@001 {
     			device_type = "cpu";
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x001>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     		cpu@100 {
     			device_type = "cpu";
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x100>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     		cpu@101 {
     			device_type = "cpu";
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x101>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     		cpu@200 {
     			device_type = "cpu";
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x200>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     		cpu@201 {
     			device_type = "cpu";
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x201>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     		cpu@300 {
     			device_type = "cpu";
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x300>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     		cpu@301 {
     			device_type = "cpu";
     			compatible = "apm,potenza", "arm,armv8";
     			reg = <0x0 0x301>;
     			enable-method = "spin-table";
    -			cpu-release-addr = <0x1 0x0000fff8>;
    +			cpu-release-addr = <0x40 0x0000f000>;
     		};
     	};

    @@ -276,7 +276,7 @@
     			compatible = "ns16550";
     			reg = <0 0x1c020000 0x0 0x1000>;
     			reg-shift = <2>;
    -			clock-frequency = <10000000>; /* Updated by bootloader */
    +			clock-frequency = <50000000>; /* Updated by bootloader */
     			interrupt-parent = <&gic>;
     			interrupts = <0x0 0x4c 0x4>;
     		};
    @@ -373,7 +373,7 @@
     			interrupts = <0x0 0x3c 0x4>;
     			dma-coherent;
     			clocks = <&menetclk 0>;
    -			local-mac-address = [00 01 73 00 00 01];
    +			local-mac-address = [00 00 00 00 00 00];
     			phy-connection-type = "rgmii";
     			phy-handle = <&menetphy>;
     			mdio {
    --
    1.9.3
pmu: Adding support for Xgene PMUs

Message-id: <1395778948-47814-2-git-send-email-ddutile@redhat.com>
Patchwork-id: 78602
O-Subject: [PATCH 1/3] pmu: Adding support for Xgene PMUs
Bugzilla: 1079110

Backport of these two posted (but not upstream) patches.
Combined into single patch due to gic-patch dependency.

Signed-off-by: Donald Dutile <ddutile@redhat.com>
rtc: ia64: allow other architectures to use EFI RTC

Currently, the rtc-efi driver is restricted to ia64 only.
Newer architectures with EFI support may want to also use
that driver. This patch moves the platform device setup
from ia64 into drivers/rtc and allow any architecture with
CONFIG_EFI=y to use the rtc-efi driver.

Signed-off-by: Mark Salter <msalter@redhat.com>
ARM: GIC: move some bits of GICv2 to a library-type file

A few GICv2 low-level function are actually very useful to GICv3,
and it makes some sense to share them across the two drivers.
They end-up in their own file, with an additional parameter used
to ensure an optional synchronization (unused on GICv2).

Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arm64: initial support for GICv3

The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
- Locality-specific Peripheral Interrupts (LPIs)
- Interrupt Translation Services (ITS)

This patch adds preliminary support for GICv3 with ARE and SRE,
non-secure mode only. It relies on higher exception levels to grant ARE
and SRE access.

Support for LPI and ITS will be added at a later time.

Cc: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Zi Shen Lim <zlim@broadcom.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arm64: GICv3 device tree binding documentation

Add the necessary documentation to support GICv3.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arm64: boot protocol documentation update for GICv3

Linux has some requirements that must be satisfied in order to boot
on a system built with a GICv3.

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
KVM: arm/arm64: vgic: move GICv2 registers to their own structure

In order to make way for the GICv3 registers, move the v2-specific
registers to their own structure.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
KVM: ARM: vgic: introduce vgic_ops and LR manipulation primitives

In order to split the various register manipulation from the main vgic
code, introduce a vgic_ops structure, and start by abstracting the
LR manipulation code with a couple of accessors.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
KVM: ARM: vgic: abstract access to the ELRSR bitmap

Move the GICH_ELRSR access to its own functions, and add them to
the vgic_ops structure.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>