verilog: Add support for SystemVerilog assertions
verilog: Use tokens to store extra identifier information
verilog: Support functions with range or type defined
verilog: Improve support of functions and tasks in SystemVerilog

In SystemVerilog function, task, etc declarations support a simple typeless port
declaration such as:

function mult(a, b);

Add support for such port declarations by searching for any non-keyword tag,
ignoring its direction and type. The same algorithm is also used in task
declarations.

Also add support for extern functions and tasks.
verilog: Create dropContext() function
verilog: Add support for SystemVerilog typdef
verilog: Add support for SystemVerilog package
verilog: Add support for SystemVerilog covergroup
verilog: Only call tagNameList in variable-like tags

Only variable-like tags can be defined in a name list split by commas, so move
all variable declaration related code to inside tagNameList function and only
call it when such kinds are found.
docs: Include SystemVerilog in new parser list