iommu: msm: Refactor code to separate compilation

Modify the code and update makefile and defconfig to allow us to
only compile one of the two IOMMU drivers that we have. Only one of
the drivers are needed at the same time. This will ensure we are not
compiling and linking code that is not needed.

Change-Id: I7db69f873245e57bddab6625e0b04e2ed48f44b6
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
iommu: msm: Cache whether the soc supports v0 IOMMUs

Currently, each call to determine if the SOC supports the v0
IOMMU makes at least one call to of_find_compatible_node. This
function is not excessively slow usually but
msm_soc_version_supports_iommu_v0 is called on the fast path which
introduces latency. Since v0 support is not something that can be
changed at runtime, cache the status of v0 support in a static variable
to avoid calling the devicetree functions frequently.

Change-Id: I835774a2cecb074f2bf25b1d3acb6fb87a5c0417
CRs-Fixed: 507473
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm: kgsl: Fix a missing semicolon in the KGSL IOMMU handler

in check_if_freed() a call to kgsl_get_memory_usage() was terminated with
a comma instead of a semicolon.  Through a quirk in a macro this somehow
managed to compile and function properly but that doesn't make it okay.

CRs-fixed: 497280
Change-Id: Ic0dedbadfdf901bbc68b7f8cefb231d08dd01a95
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Option to not stall IOMMU V1 on pagefault based on FT policy

There are cases where GPU has a pagefault and executes
fine after pagefault without GPU stall. init.qcom.graphics.sh
script can be used to change FT pagefault policy
to not stall IOMMU V1 on pagefault and check if pagefault is harmless.

Change-Id: If061230b66181bfd94c697ea106e7bf4de352e91
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
msm: kgsl: Fix addressing of FSYNR0 and FSYNR1 registers

Fix the addressing of FSYNR0 and FSYNR1 IOMMU-v1 registers. These
are context registers and were being addressed as global registers.

Change-Id: I2f6c4798a3c82bb4857a334beb99994ac9f4a1e8
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
msm: kgsl: Fix checking of returned error

IOMMU get context functions return error as a pointer so just
checking for NULL is not correct. Use the right macro to check
if error is returned and only force initialization of one context
for IOMMU-v1 since other contexts are not used.

Change-Id: I5123363567649568127e24738f19ea30f98a6cec
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
msm: kgsl: Do not register additional IOMMU faults

When an IOMMU fault occurs the fault is cleared in a
queued work item. Until the queued item runs the system
will report the same fault over and over again. Ignore
these faults until the original fault is cleared in the
queued work item.

Change-Id: I96a63ab8f568a874f25da0c56d1e3d8cf7e73e6c
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
msm: kgsl: Set FSR to 0 on IOMMU pagefault

On IOMMU pagefault the FSR is not cleared until the IOMMU
is reset and re-attached to the GPU device. Until FSR clears
the system will keep generating fault interrupts. Clear the
FSR when iommu is stopped in kgsl driver to prevent system
from generating additional fault interrupts for the same
fault until the IOMMU is re-attached

Change-Id: Ia56bbd1245a84a001ec8464f73cfedf2a2d312c2
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
msm: kgsl: Enable the iommu halt feature for certain IOMMU versions

Enable the IOMMU halt feature for non v0 IOMMU versions instead of
depending on the feature being enabled in the IOMMU device tree.
This is because on certain chipsets this feature is not set in
the device tree even if the IOMMU h/w supports it.

Change-Id: I39236b5f7a7dc1d0d739bbb39bfc7fda4931da56
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
msm: kgsl: Check return value on waiting for GPU to idle

Use the return value of kgsl_idle to do smart things rather than
just ignoring it.

Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
FIX drivers/gpu/msm/kgsl_iommu.c missing ret
iommu: msm: Add decoding to PAR when fault occurs

Add decoding of the PAR register when a VA2PA translation fault
occurs to help in debugging.

Change-Id: Ie3c442d29c3c10f7437acbb63262eb51bc9cc9ab
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
iommu: Do not clear FSR if fault handler returns EBUSY

If the IOMMU unit's driver returns EBUSY from fault handler then
do not clear the FSR. This will prevent the IOMMU unit from
unstalling itself. Some driver like graphics need for the IOMMU
to be stalled until that driver is ready to clear it.

Change-Id: Ic2b846dbba93d1b706309705e04d93f6c803bd2b
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
msm: iommu: remove tlb_invalidate from the map calls

TLB_invalidate calls are not required as we are not changing the
mapping, but creating a new one. So, remove unnecessary invalidation
from the map calls.

Change-Id: I72f9f1cce341c3dc92e2819dd7a4d2e032909e7b
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
iommu: msm: zero out the bus_client in __put_bus_vote_client

The bus_client variable might become stale and re-used later. This is
causing a kernel panic when enabling bus votes on iommu v1. Fix this
by zero'ing out the variable as it's done in msm_iommu_dev-v0.c

CRs-fixed: 483497
Change-Id: Ib34a2f25d9eff0deee2e3809c6736ce2832e445f
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Tune Default Ondemand config.
gpu: ion: Add page pooling to the iommu heap

The system heap currently supports pooling of uncached pages
to avoid the cost of zeroing/flushing the pages every time.
Add similar functionality to the iommu heap for both cached
and uncached pages. The cached pages won't see the benefit of
delayed cache syncing but they will see a benefit for zeroing
of the buffers and reduced allocation time. Some clients may
wish to always get pages from the allocator instead of going
through the pool so add a flage to support that feature.

Change-Id: Id972d12c18a940c4eb52553a9cb7658fd1d24a26
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>

Conflicts:
	drivers/gpu/ion/ion_iommu_heap.c
gpu: ion: Ensure zeroed memory gets written to RAM

When zeroing buffers, we need to make sure the zeroed data actually
gets written back to RAM. Otherwise, it may be possible for a buffer
to be reallocated with data still needing to be written back to RAM.
This may lead to corruption from userspace allocators expecting zero'd
buffers and a potential leak of kernel data to user space. Considering
the mapping is short lived and we need to write back the data, use a
writecombine mapping to write the data directly to ram and avoid the
cost of flushing the cache. If the mapping is cached, invalidate the
kernel side mappings as well.

Change-Id: I26a49908bde411469f3b8f143a1581fb4e2c3b56
CRs-Fixed: 520044
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
gpu: ion: Set the dma address for pages from the page pool

In order to properly call dma_sync_sg_for_device, the dma address
must be set on each scatterlist. When manually creating sg lists from
individual pages, the dma address must be set manually, else the cache
flushing will not succeed. Set the dma address of the sg list for
uncached page flushing to ensure the pages get completely flushed.

Change-Id: I1b89b5e2bd5ba75e7340c347eab256acec7d9554
CRs-Fixed: 496298
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
gpu: ion: switch to using kmalloc for the secure chunk list

When securing buffers for secure content playback, a list of 1MB
chunks is generated. The number of buffers that will ever be in this
list will never be more than 1024, which means the buffer list will
always be less than a page. Rather than use the contiguous APIs, just
use the slab allocator to get the physical address list. The slab will
be physically contiguous and appropriate to pass to TZ.

Change-Id: Ib3f7293fbe0e5db872c9c441645ca860cc9bb9ff
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>