[CORE] Don't compile vmm_modules if CONFIG_MODULES is not set

Also changed MODULES to CONFIG_MODULES in the menuconfig.

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[TOOLS] openconf: Depend on CONFIG_MODULES symbol instead of MODULES

We should be using CONFIG_MODULES symbol for runtime loadable module
for consistency accross Xvisor code hence we update openconf to look
for CONFIG_MODULES symbol instead of MODULES symbol for tristate
options.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARCH] Rename MODULES=y to CONFIG_MODULES=y in all defconfigs

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Only disable runtime module loading/unloading when CONFIG_MODULES=n

Currently, if we disable runtime module loading/unloading (i.e.
CONFIG_MODULES=n) then vmm_modules.c is not compiled at all. This
means no modules will be initialized at boot-time even if the modules
are meant to be built-in. Also, Xvisor ARM crashes because it tries to
call RTC APIs without initializing RTC module.

The linux-compatible meaning of CONFIG_MODULES=n is to only disable
runtime module loading/unloading but built-in modules are still allowed.

This patch selectively compiles out lot of code when CONFIG_MODULES=n
instead of not compiling vmm_modules.c. This saves us roughly 40-50KB
on Xvisor ARM when CONFIG_MODULES=n and also allows built-in modules
when CONFIG_MODULES=n.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_host_irq: Process multiple active IRQs from vmm_host_irq_exec()

Currently, we only process on interrupt in vmm_host_irq_exec(). This is
not optimal because we might have multiple interrupts pending in irqchip.

This patch renames vmm_host_irq_exec() to vmm_host_active_irq_exec() and
improves it to process all pending interrupts in irqchip.

Signed-off-by: Anup Patel <anup@brainfault.org>
[DRIVERS] irqchip: Use EOImode for GIC with virtualization extensions

We need to support host-to-guest irq routing in VGIC. To do that, the
GICv2 spec recommends us to use EOImode. To enable EOImode, we need to
set GICC_CTRL.EOImodeNS bit for each acitive GIC CPU interface.

When GICC_CTRL.EOImodeNS==1, the end-of-interrupt is divided into two
steps, which are:
1. De-prioritize the interrupt by writing the irq number to GICC_EOI
register
2. De-activate the interrupt by writing the irq number to GICC_DIR
register

When GICC_CTRL.EOImodeNS==0, the end-of-interrupt is just one step
that is writing irq number to GICC_EOI register.

For rounting irq from host to guest, we need to do the following:
1. Take interrupt in hypervisor with EOImode enabled (i.e.
GICC_CTRL.EOImode==1)
2. Upon receipt of routed host irq, only de-prioritize it but don't
de-activate it. (i.e. only write host irq number to GICC_EOI register)
3. Queue the host irq as virtual guest irq with maintainence interrupt
enabled using GICH_LRx registers.
4. When guest writes to GICV_EOI register after handling guest irq
we will get maintainence interrupt.
5. Upon receipt of maintainence interrupt for guest irq, de-activate
the host irq by writing host irq number to GICC_DIR register.

This patch changes the GIC driver to use EOImode for GIC with
virtualization extensions so that we can implement host-to-guest
irq routing in VGIC driver.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Use unsigned long instead of u32 for vmm_delay APIs

Currently, we use u32 parameters for vmm_delay APIs which means
even on 64bit host we will endup implementing arch_delay_xxxx()
using 32bit registers.

This patch updates all vmm_delay APIs to use unsiged long instead
of u32 so that we can use unsigned long for arch_delay_xxxx(). This
will help us use 64bit registers on 64bit host for implementing
arch_delay_xxxx() functions.

Signed-off-by: Anup Patel <anup@brainfault.org>
[DRIVERS] irqchip: Reduce dependency of GIC driver on irq_start parameter

Currently, the GIC irqchip driver depends more on irq_start parameter
passed via device tree node. This irq_start parameter/attribute is
non-standard and can be assumed based on GIC instance is primary
or secondary. For example, if GIC is primary interrupt controller
then irq_start can be safely assumed to be 16 whereas for secondary
GIC irq_start can be assumed to be 32.

This patch simplifies GIC irqchip driver to reduce dependency on the
irq_start parameter/attribute.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: Don't use maintainence interrupt for EOIed LRs

Currently, we programme LR registers such that we get maintainence
interrupt for EOIed level-triggered interrupt. Unfortunately most
of the ARM Guest interrupts are generally level-triggered hence
we get a maintainence interrupt for every interrupt injected to
Guest VCPU and we re-claime EOIed LRs when processing maintainence
interrupt. Due to this kind of maintainence interrupt usage we
end-up wasting lot of CPU time in processing maintainence interrupt.

This patch improves the VGIC code by avoiding usage of maintainence
interrupt for re-claiming EOIed LRs. Now instead of maintainence
interrupt we re-claim EOIed LRs when injecting virtual interrupt
in vgic_handle_irq().

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] generic: sun4i: Move aliases node to sun4i-a10.dtsi

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] generic: sun7i: Reorganize DTS files to support multiple sun7i boards

This patch mostly reorganizes DTS files for sun7i soc such that we can add
more DTS board specific DTS files later.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Return more error information from vmm_vcpu_irq_wait_resume()

Currently, we are skipping lot of error scenarios while returning
from vmm_vcpu_irq_wait_resume() (i.e. vmm_vcpu_irq_wait_resume()
silently returns VMM_OK for those skipped error scenarios). If
vmm_vcpu_irq_wait_resume() returns error codes for all failure
cases then it will be helpful to the caller to do something when
vmm_vcpu_irq_wait_resume() fails.

This patch updates vmm_vcpu_irq_wait_resume() to capture more
failure cases.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Add vmm_manager_vcpu_hcpu_resched() & vmm_manager_vcpu_hcpu_func() APIs

This patch adds two new useful APIs to vmm_manager for SMP host:
1. vmm_manager_vcpu_hcpu_resched() - This API forces rescheduling on the
host CPU assigned to given VCPU.
2. vmm_manager_vcpu_hcpu_func() - This API helps us call a function on
the host CPU assigned to given VCPU.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: SGI sources and IRQ-to-LR mapping improvments

This patch does minor improvements to:
1. Per-VCPU SGI sources used to trigger SGIs: We need to
protect the per-VCPU SGI sources hence me move "sgi_sources"
from struct vgic_vcpu_state to struct vgic_guest_state and
protect it using "dist_lock".
2. Per-VCPU IRQ-to-LR mapping: Currently we only mapped
each IRQ to LR assigned to it. Instead this should be
(IRQ, Source CPU) mapped to assigned LR for capturing
software triggered interrupts.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: Minor performance improvements

This patch two performance improvements:
1. Treat all SGIs (i.e. irq < 16) as edge-triggered and
don't touch pending flag for edge-triggered interrupts
in __vgic_sync_vcpu_hwstate()
2. No need to test VGIC_TEST_ENABLED() along with
VGIC_TEST_PENDING() because an irq can only be pending
if it is enabled.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: Map CPU interface registers for upcoming irq routing

For routing physical interrupts to guest, we would require to exploit
the EOImode to de-prioritize physical interrupts and de-activate
physical interrupts from guest using HW bit of GICH_LRx registers.

To do the above, we would require to access GICC_EOI and GICC_DIR
register from VGIC driver hence this patch is a preparatory patch
for upcoming irq routing in VGIC.

Signed-off-by: Anup Patel <anup@brainfault.org>
[DRIVERS] fix return code in timer

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[CORE] Mandate emulator for both real and virtual device regions

Generally, we use manifest_type=virtual and
device_type!=(ram|alloced_ram|rom|alloced_rom) for
specifying emulated/virtual device.

We would be using manifest_type=real and
device_type!=(ram|alloced_ram|rom|alloced_rom) for
specifying real/pass-through device.

In addition to above, a pass-through/real device would
also require configuring IOMMU/SMMU before the device
is accessed by Guest. Upon Guest reset we might also
require to cleanup/reset device state because Guest OSes
typically don't cleanup device state on reset.

To tackle, the above we mandate emulator for both
real and virtual devices. This means for having
pass-through access to a device we will require
a emulator for it which will handle setup and
cleanup or pass-through device.

This patch updates vmm_guest_aspace and vmm_devemu
to achieve the above.

Also, this patch will break guest creation for guest
requiring VGIC hence subsequent patches fixes VGIC
emulator for allowing pass-through access to VGIC
virtual CPU interface.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: Register separate emulators for dist and cpu interface

Now we need to provide emulator for pass-through access to VGIC
virtual CPU interface hence this patch updates VGIC code to provide
two separate emulators for Guest GIC dist and Guest GIC cpu interfaces.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] No need to specify host physical address for VGIC CPU interface

Updated VGIC emulator registers separate emulator for VGIC CPU interface
which automatically updates the host physical address in Guest VGIC CPU
region hence we don't need to explicity specify it via device tree.

Signed-off-by: Anup Patel <anup@brainfault.org>