[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.

Summary:
The linked-load, store-conditional operations have been re-encoded such
that have a 9-bit offset instead of the 16-bit offset they have prior to
MIPS32r6/MIPS64r6.

While implementing this, I noticed that the atomic load/store pseudos always
emit a sign extension using sll and sra. I have improved this to use seb/seh
when they are available (MIPS32r2/MIPS64r2 and above).

Depends on D4118

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211018 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6

Summary:
There is no change to the restrictions, just the result register is stored
once in the encoding rather than twice. The rt field is zero in
MIPS32r6/MIPS64r6.

Depends on D4119

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4120

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211019 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6

Summary: Depends on D4120

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: zoran.jovanovic, vmedic

Differential Revision: http://reviews.llvm.org/D4121

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211021 91177308-0d34-0410-b5e6-96231b3b80d8
Hook up vector int_ctlz for AVX512.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211024 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Remove dead code.

Both function declarations lack a callee and an implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211029 91177308-0d34-0410-b5e6-96231b3b80d8
Convert the Archive API to use ErrorOr.

Now that we have c++11, even things like ErrorOr<std::unique_ptr<...>> are
easy to use.

No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211033 91177308-0d34-0410-b5e6-96231b3b80d8
Fix pr17056.

This makes llvm-nm ignore members that are not sufficiently aligned for
lib/Object to handle.

These archives are invalid. GNU AR is able to handle this, but in general
just warns about broken archive members.

We should probably start warning too, but for now just make sure llvm-nm
exits with an 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211036 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor the disabling of Thumb-1 LDM/STM generation

Originally I switched the LD/ST optimizer off in TargetMachine as it was previously, but Eric has suggested he'd prefer that it be short-circuited in the pass itself.

No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211037 91177308-0d34-0410-b5e6-96231b3b80d8
LowerSwitch: track bounding range for the condition tree.

When LowerSwitch transforms a switch instruction into a tree of ifs it
is actually performing a binary search into the various case ranges, to
see if the current value falls into one cases range of values.

So, if we have a program with something like this:

switch (a) {
case 0:
  do0();
  break;
case 1:
  do1();
  break;
case 2:
  do2();
  break;
default:
  break;
}

the code produced is something like this:

  if (a < 1) {
    if (a == 0) {
      do0();
    }
  } else {
    if (a < 2) {
      if (a == 1) {
        do1();
      }
    } else {
      if (a == 2) {
        do2();
      }
    }
  }

This code is inefficient because the check (a == 1) to execute do1() is
not needed.

The reason is that because we already checked that (a >= 1) initially by
checking that also  (a < 2) we basically already inferred that (a == 1)
without the need of an extra basic block spawned to check if actually (a
== 1).

The patch addresses this problem by keeping track of already
checked bounds in the LowerSwitch algorithm, so that when the time
arrives to produce a Leaf Block that checks the equality with the case
value / range the algorithm can decide if that block is really needed
depending on the already checked bounds .

For example, the above with "a = 1" would work like this:

the bounds start as LB: NONE , UB: NONE
as (a < 1) is emitted the bounds for the else path become LB: 1 UB:
NONE. This happens because by failing the test (a < 1) we know that the
value "a" cannot be smaller than 1 if we enter the else branch.
After the emitting the check (a < 2) the bounds in the if branch become
LB: 1 UB: 1. This is because by checking that "a" is smaller than 2 then
the upper bound becomes 2 - 1 = 1.

When it is time to emit the leaf block for "case 1:" we notice that 1
can be squeezed exactly in between the LB and UB, which means that if we
arrived to that block there is no need to emit a block that checks if (a
== 1).

Patch by: Marcello Maggioni <hayarms@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211038 91177308-0d34-0410-b5e6-96231b3b80d8
Fix illegal relocations in X86FastISel

On x86_86  the lea instruction can only use a 32 bit immediate value. When
the code is compiled statically the RIP register is not used, meaning the
immediate is all that can be used for the relocation, which is not sufficient
in the case of targets more than +/- 2GB away. This patch bails out of fast
isel in those cases and reverts to DAG which does the right thing.

Test case included.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211040 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: implement correct atomic operations on v7M

ARM v7M has ldrex/strex but not ldrexd/strexd. This means 32-bit
operations should work as normal, but 64-bit ones are almost certainly
doomed.

Patch by Phoebe Buckheister.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211042 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "lit: warn when passed invalid pathname" (r210597)

It was pointed out that this breaks the "virtual test discovery"
mechanism, which allows for narming tests in the test exec root.

Reverting until I can figure out how to fix this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211048 91177308-0d34-0410-b5e6-96231b3b80d8
Improve comments for r211040

Added comment to clarify why we r211040 choose to bail out of fast isel instead
of generating a more complicated relocation, and fix mislabelled register in the
comments of the asan test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211052 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up some unnecessary mutex guards.

These were being used as unreferenced parameters to enforce that
the methods must not be called without holding a mutex, but all
of the methods in question were internal, and the methods were
only exposed through an interface whose entire purpose was to
serialize access to these structures, so expecting the methods
to be accessed under a mutex is reasonable enough.

Reviewed by: blaikie

Differential Revision: http://reviews.llvm.org/D4162

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211054 91177308-0d34-0410-b5e6-96231b3b80d8
Since the DataLayout is always found off of the subtarget go ahead
and query the base target machine implementation for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211055 91177308-0d34-0410-b5e6-96231b3b80d8
[PPC64] Fix PR19893 - improve code generation for local function addresses

Rafael opened http://llvm.org/bugs/show_bug.cgi?id=19893 to track non-optimal
code generation for forming a function address that is local to the compile
unit.  The existing code was treating both local and non-local functions
identically.

This patch fixes the problem by properly identifying local functions and
generating the proper addis/addi code.  I also noticed that Rafael's earlier
changes to correct the surrounding code in PPCISelLowering.cpp were also
needed for fast instruction selection in PPCFastISel.cpp, so this patch
fixes that code as well.

The existing test/CodeGen/PowerPC/func-addr.ll is modified to test the new
code generation.  I've added a -O0 run line to test the fast-isel code as
well.

Tested on powerpc64[le]-unknown-linux-gnu with no regressions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211056 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: intrinsic support for rbit.

We already have an ARMISD node. Create an intrinsic to map to it so we can
add support for the frontend __rbit() intrinsic.

rdar://9283021

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211057 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: Add backend intrinsic for rbit.

Define an intrinsic for the frontend to use and pattern match it to
the RBIT instruction.

rdar://9283021

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211058 91177308-0d34-0410-b5e6-96231b3b80d8
Add load/store functionality

Summary:
This patches allows non conversions like i1=i2; where both are global ints.
In addition, arithmetic and other things start to work since fast-isel will use
existing patterns for non fast-isel from tablegen files where applicable.

In addition i8, i16 will work in this limited context for assignment without the need
for sign extension (zero or signed). It does not matter how i8 or i16 are loaded (zero or sign extended)
since only the 8 or 16 relevant bits are used and clang will ask for sign extension before using them in
arithmetic. This is all made more complete in forthcoming patches.

for example:
  int i, j=1, k=3;
 
  void foo() {
    i = j + k;
  }

Keep in mind that this pass is not enabled right now and is an experimental pass
It can only be enabled with a hidden option to llvm of -mips-fast-isel.

Test Plan: Run test-suite, loadstore2.ll and I will run some executable tests.

Reviewers: dsanders

Subscribers: mcrosier

Differential Revision: http://reviews.llvm.org/D3856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211061 91177308-0d34-0410-b5e6-96231b3b80d8
Users of the llvm global mutex must now acquire it manually.

This allows the mutex to be acquired in a guarded, RAII fashion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211066 91177308-0d34-0410-b5e6-96231b3b80d8