sim_core: fixes and reductions

correct a few goofed up opcode descriptions.

get_d5 and get_r5: remove trailing slash on last macro line

add get_vd5: get_vd5 pulls in from get_d5 plus loads from register...
	removes one definate instance of a possible double load, also
	potentially removes double loads during tracing.

get_d5_b3 changed to get_vd5_b3: as all instances use the value of
	reg d.  get_vd5_b3 pulls in from get_vd5.  reduces one definate
	instance for potential of double loads and possibly reducing
	the potential during tracing.

add get_vd5_b3_mask: two instances use b3 as a mask, get_vd5_b3_mask
	pulls in from get_vd5_b3.

add get vh4_k8: get_vh4_k8 pulls in from get_h4_k8, removes the extra
	line to pull in from the register...  removes possible double
	load during tracing.

get_p2_k6 changed to get_vp2_k6: register load was moved into the macro
	as both instances need the value loaded from the register pair.

add get_io5 and get_io5_b3mask: get io5_b3 and get_io5_b3mask pulls in
	from get_io5...  most instances using get_io5_b3 take bit
	number and use it as a mask, get_io5_b3mask does that by default.

get_o12: rcall and rjmp both left shift the value back before using
	the offset...  the macro just calls for one less bit to be
	shifted...  during trace we then make the extra shift as needed.

	modified:   sim/sim_core.c
Merge pull request #71 from bsekisser/master-core-fixes-reductions

sim_core: fixes and reductions
cores: Fix ADCH and ADCL to use defines for RFA1

No current release provides these defines however they are fixed in
avr-libc trunk and as such we should use them if they are available.
Clean up outdated comment

This comment is no longer true for any of the listed platforms so its
best to adjust the wording to what might be relevant to users
cores: Add initial support for ATmega128RFR2

Add initial support for the ATmega128RFR2 which according to Atmel is a
drop in replacement for the ATmega128RFA1 however in real world testing
I have found this to not be entirely true. All of the changes (new
features) added to the R2 are not exposed with current simavr
peripherals so this file is identical to the A1 in simavr.
cores: RFA1/RFR2 don't have Port A and Port C

The ATmega128RFA1 and ATmega128RFR2 don't actually have Port A and Port
C as IO pins.
Merge pull request #72 from cardoe/rfr2

Support for ATmega128RFR2
cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2

PCINT8 was previously not setup. Per the spec sheet it is on Port E pin
0.
Merge branch 'master' into merged
Merge branch 'rfa1-rfr2-pcint8' into merged
cores: Fix fuse support to handle proper byte size

avr-libc specifies platforms with only 6, 3, 2, 1, and 0 bytes of fuses.
Previously simavr only had 4 bytes available for fuses and assumed any
platform using the CORE_DECLARE macro would have 3 fuses. This change
allows the CORE_DECLARE macro to support any of the platforms supported
by avr-libc with regard to fuses. Additionally add some defines to make
it clear for users of simavr what order the fuses are in.
cores: Add a field for Lock Bits and Boot Lock Bits

Add an extra byte for allowing simavr store the chip's lock bits / boot
lock bits as well as set the default value as defined in a number of
specs.
elf: Wire up support for Fuses and Lock Bits

Support reading fuses and lock bits from ELF files and loading them into
the simavr internals for later use.
elf: Clean up code duplication and fix a cast

Use the helper function elf_copy_section() to get rid of some code
duplication and use the correct printf() type so that there is no cast
necessary.
elf: check for error instead of crashing

Check for error when allocating memory instead of dereferencing a NULL
pointer later in the program.
Merge branch 'fuses-lockbits' into merged