freedreno: few caps fixes

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/a3xx: texture fixes

Signed-off-by: Rob Clark <robclark@freedesktop.org>
mesa/st: fix color outputs in presence of sample mask output

Commit c5d822dad90 added support for sample mask incorrectly. It became
treated as a color output, and messed up the color output indices.
Revert the hunk that did that, and add explicit support just like for
depth/stencil writes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
nvc0: revert mistaken logic to collapse color outputs to the beginning

In commit af38ef907, I added a "fix" to color outputs not being assigned
correctly when sample mask was being output. This was totally wrong --
the color indices (i.e. "si" values) were the ones that were wrong. Undo
that hunk.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
Revert "i965/fs: Reduce restrictions on interference in register coalescing."

This reverts commit f770123f58b46459e8dbd27525162ee8ba89f30b.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78692
Revert "i965/fs: Give up in interference check if we see a WHILE."

This reverts commit 55de1c035cbca2b7087b3aa21a8c3dfc900a4ad9.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Revert "i965/fs: Simplify interference scan in register coalescing."

This reverts commit 5ff1e446d44bb9d50f84883c7058635cb070e069.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77704
Revert "i965: Don't make instructions with a null dest a barrier to scheduling."

This reverts commit 42a26cb5e441a01d5288b299980f23affaad53fe.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78648
i965: Switch types D->UD when possible to allow compaction.

Number of compacted instructions: 827404 -> 833045 (0.68%)

Reviewed-by: Eric Anholt <eric@anholt.net>
nvc0: implement clear_buffer

Provide an accelerated path for ARB_clear_buffer_object

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
i915g: handle more formats in copy

We can handle depth, luminance,... copies by simply replacing the
format with a known format of the same bpp.
i915g: Fallback to sw for npot copies

i915g's npot support is incomplete, so let's not use it for copies.
This fixes a bunch of piglit tests.
i915g: Fix shader disasm code

This broke when I separated declarations/shader.
meta/blit: Add stencil texturing mode save and restore

v2 (Ken): Only restore the mode if it has changed.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/meta: Store stencil texturing mode

Meta path needs to keep the current texture object's state. Fixes
the following gles3 cts tests on bdw:

framebuffer_blit_functionality_negative_width_blit.test: fail
framebuffer_blit_functionality_all_buffer_blit.test: fail
framebuffer_blit_functionality_negative_height_blit.test: fail
framebuffer_blit_functionality_missing_buffers_blit.test: fail
framebuffer_blit_functionality_negative_dimensions_blit.test: fail
framebuffer_blit_functionality_minifying_blit.test: fail
framebuffer_blit_functionality_magnifying_blit.test: fail

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
vl: add interface for non-referenced frames

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
radeon/vce: implement non-referenced frames

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
st/omx/enc: implement restricted b frames pattern

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
i965/sf: Reset flag_value to 0xff before emitting SF subroutines.

When compiling any of the SF program variants, flag_value starts off as
0xff and will be modified when generating code.

brw_emit_anyprim_setup emits several subroutines, saving and restoring
flag_value across each of them.  Since it starts out as 0xff, this is
equivalent to simply setting it to 0xff at the start of each subroutine.

Resetting the value makes more logical sense; each subroutine doesn't
know whether one of the others even executed, much less what it did
to the flag register.

This also lets us to drop the brw_set_predicate_control_flag_value call
from brw_init_compile: predicate is already initialized to
BRW_PREDICATE_NONE by the memset, and the value of flag_value is
irrelevant (as it's only used by the SF compiler).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>