clk: sunxi: fix mux clk takes register bit mask instead of width

clk_register_mux takes both register bit shift and mask as parameters
to which bits it should use to control the clock mux.

sunxi_mux_clk_setup incorrectly passed the width of effective bits,
instead of the bit mask. This would result in incorrect values being
read or set.

Fixes: e874a6697710 ("clk: arm: sunxi: Add a new clock driver for sunxi SOCs")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: stable@vger.kernel.org