Commit prior to ioc change/rebuild.
New STM32CubeMX ioc.
Snapshot of current configuration - Strangeness abounds in USART3/SPI impl.
Workaround for USART_TC strangeness.  Seems like we have to wait until the second interrupt to consider the transaction complete - problematic.
HAL-bug: FIFO Threshold interrupt/DMA error being triggered.  ...But we aren't using the FIFO.
Vast improvement with USART3 behavior.
Removed vestages of USART_TC interrupt code.
HAL Edit to ensure OVER8 is enabled in USART (Sampling at all is kinda dumb, since we're in control of the clock, directly.)

BaudRate of 1750000 appears to be yielding what USART3 is capable of.  In the future, USART1/6 are better choices for communications, or a dedicated SPI.