hdl: Added ATSC TX FPGA implementation

This revision introduces an FPGA-based ATSC transmitter to offload the
pilot insertion, filtering, and shift to baseband.

This design expects that 4-bit ATSC symbols are written to the device in
little-endian 32-bit words, as shown below.

        |<-------                               32 Bit Word                                     ------->|
Bit     |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
Symbol  [ X|   7    ][X|  6     ][X|   5    ][X|    4   ][X|   3   ][X|   2     ][X|    1   ][X|    0   ]

The FPGA transmits Symbol 0 first, and Symbol 7 last. The three
least-significant bits in each symbol's nibble contain values 0 to 7,
mapping to values of -7 to 7, with the most-significant bit left unused.

This FPGA image may be built by specifying the "atsc_tx" image to the
build_bladerf.sh script. The resulting output files will be
atsc_txx40.rbf and atsc_txx115.rbf for the x40 and the x115,
respectively.

Transmitting a pre-made stream on channel 14-1 can be achieved with the
following commands in the bladeRF-cli:

    set frequency 473000000
    set samplerate 32286713 2867 10000

    set txvga1 -4
    set txvga2 20

    tx config file=<path to file> repeat=0 delay=0
    tx start