msm: mdss: Add SMP parameters into hw capabilites

To handle use cases better, expose smp_mb_cnt and
smp_mb_per_pipe to userspace as part of hardware capability.
Pipes availablity for a use case can be computed taking these
values, based on which, composition decisions can be made.

Change-Id: Ia7cc4db153cdb164a29ae2369d3e991b95aaba65
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm: mdss: Add backlight attenuation mechanism in AD auto strength mode

AD backlight attenuation provides the ability to modulate backlight based
on calibration before feeding it to AD core for strength computation.

Change-Id: Iea011807b25882463b1142e17324fa0509007aa4
Signed-off-by: Ping Li <quicpingli@codeaurora.org>
PM / devfreq: Make target flags unique

Overlapping target flags cause both to be set
rather than the intended one.  Make sure the flags
have different values.

Change-Id: Ia4fb9566be7284e57e67be78c32de05cbd11d6f8
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
drivers: cpufreq: Send a uevent when governor changes

 * Useful so userspace tools can reconfigure.

Change-Id: Ib423910b8b9ac791ebe81a75bf399f58272f64f2
cpufreq: Fix broken uevents for cpufreq governor and cpu devices

cyanogens uevent commit when the governor changes was rendered
non-working since kitkat (or so) as the uevent filter function
caused events to be dropped. Now hook into cpufreq_core_init()
and cpufreq_add_dev_interface() to create our basic ksets for
cpufreq and cpu devices. Also, we don't need to set environmental
data, so clean it up a bit.

This commit requires a change in ueventd.rc that add rules for
several files of interest.

Change-Id: I3aafa0d4e18363e1d68535f513099ecd27024007
genalloc: Correct nbytes calculation on long boundary

In existing code we calculate nbytes based on the byte
boundary, but genalloc uses bitmap for maintaining the
memory allocation aligned to long. So while calculating
nbytes we end up getting wrong nbytes.
example: lets say nbytes comes to 9 bytes for 70 bits when
bytes aligned,but if long aligned we will have 3 long words
i.e 12 bytes. This difference may lead to choosing the
wrong api for freeing the memory i.e Between kfree() and
vfree().
Fix was inspired by an upstream commit
eedce141cd2dad8d0cefc5468ef41898949a7031, bringing same fix
into the gen_pool_detroy path.

Change-Id: I942caf59e25515c780896b328b912604df9e10bf
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
msm: lpm_levels: Fix incorrect computation of next wakeup time

The next event timer wakeup was incorrectly computed when the hard timer
event doesn't exist. Fix by ensuring the next wakeup is computed only
when a timer event is valid

Change-Id: I40c1f372f84d8f43b2101e37dcfb592193d4b2e0
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: mpm-of: fix for "cxo_lpm_clk is unbalanced" slowpath warning.

The variable xo_enabled needs protection. It might get called
simultaneously from suspend and mpm worker thread context.
Added a mutex to prevent this.

WARNING: at kernel/arch/arm/mach-msm/clock.c:411 clk_disable+0xc8/0x150()
cxo_lpm_clk is unbalanced
Modules linked in: adsprpc texfat(PO) mwlan_aarp(PO)
[<c010d24c>] (unwind_backtrace+0x0/0x138) from [<c01a0408>]
(warn_slowpath_common+0x4c/0x64)
[<c01a0408>] (warn_slowpath_common+0x4c/0x64) from [<c01a04b4>]
(warn_slowpath_fmt+0x30/0x40)
[<c01a04b4>] (warn_slowpath_fmt+0x30/0x40) from [<c011a068>]
(clk_disable+0xc8/0x150)
[<c011a068>] (clk_disable+0xc8/0x150) from [<c0180568>]
(msm_mpm_sys_low_power_modes+0x28/0x84)
[<c0180568>] (msm_mpm_sys_low_power_modes+0x28/0x84) from [<c0180768>]
(msm_mpm_work_fn+0x1c/0x5c)
[<c0180768>] (msm_mpm_work_fn+0x1c/0x5c) from [<c01b9568>]
(process_one_work+0x128/0x490)
[<c01b9568>] (process_one_work+0x128/0x490) from [<c01b9c14>]
(worker_thread+0x164/0x35c)
[<c01b9c14>] (worker_thread+0x164/0x35c) from [<c01be9a8>]
(kthread+0x88/0x94)
[<c01be9a8>] (kthread+0x88/0x94) from [<c0107a04>]
(kernel_thread_exit+0x0/0x8)
---[ end trace d18a7d72e45b272f ]---
------------[ cut here ]------------
WARNING: at kernel/arch/arm/mach-msm/clock.c:436 clk_unprepare+0xac/0xd4()
cxo_lpm_clk is unbalanced (prepare)
Modules linked in: adsprpc texfat(PO) mwlan_aarp(PO)
[<c010d24c>] (unwind_backtrace+0x0/0x138) from [<c01a0408>]
(warn_slowpath_common+0x4c/0x64)
[<c01a0408>] (warn_slowpath_common+0x4c/0x64) from [<c01a04b4>]
(warn_slowpath_fmt+0x30/0x40)
[<c01a04b4>] (warn_slowpath_fmt+0x30/0x40) from [<c011aa78>]
(clk_unprepare+0xac/0xd4)
[<c011aa78>] (clk_unprepare+0xac/0xd4) from [<c0180570>]
(msm_mpm_sys_low_power_modes+0x30/0x84)
[<c0180570>] (msm_mpm_sys_low_power_modes+0x30/0x84) from [<c0180768>]
(msm_mpm_work_fn+0x1c/0x5c)
[<c0180768>] (msm_mpm_work_fn+0x1c/0x5c) from [<c01b9568>]
(process_one_work+0x128/0x490)
[<c01b9568>] (process_one_work+0x128/0x490) from [<c01b9c14>]
(worker_thread+0x164/0x35c)
[<c01b9c14>] (worker_thread+0x164/0x35c) from [<c01be9a8>]
(kthread+0x88/0x94)
[<c01be9a8>] (kthread+0x88/0x94) from [<c0107a04>]
(kernel_thread_exit+0x0/0x8)
---[ end trace d18a7d72e45b2730 ]---

CRs-fixed: 596765
Change-Id: Ibe685e8f37eb63c4e9e9d3434719985f33c63376
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
cpufreq: Sync on thread migration optimizations

When threads migrate between CPUs the destination CPU will temporarily
have a boosted frequency and the source CPU will have a residual higher
frequency even though the load could have just been reduced. To avoid
leaving CPUs at a high frequencies notify the source CPU after a thread
migration and make the interactive governor's timer reschedule
conditionally.

Change-Id: Id55055f2a116ca7ffd2a34dc3d0ec519c888a111
Signed-off-by: Patrick Cain <pcain@codeaurora.org>
msm: clock: Add parent fields to gcc_ce1_clk and gcc_ce2_clk

The votable CE core clocks should be linked up to their
parents. Add the parent fields to these clocks for
MSM8974, MSM8226, and MSM8610.

CRs-Fixed: 572028
Change-Id: Ia5567b2832cdb97f08052017d314f00dbdd41133
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>