Vtests: fix step
add hasSRAM & sramMaxSize for custom transforms
parametrization in custom transforms
recover markComponent in addModule
Merge branch 'master' of https://github.com/ucb-bar/chisel into Vtests
small changes in parameterization
Merge branch 'master' into Vtests

Conflicts:
	src/main/scala/Verilog.scala
Merge pull request #283 from ucb-bar/Vtests

Fix verilog harness and add parametrization in custom transforms