several changes to the galpal

The 22V10 part works now. (managed to verify this on actual hardware).
There's timing for several speed grades(just include the appropriate header). Verilog still has problems simulating as it can only use one parameter(min, avg or max), not min/max at the same time. 
Test vector generator. including the module in the testbench and running the simulation will print vectors suitable for PLD testing.