begin pruning old CPU implementation out
finish gutting out CPU in preparation for making it table driven.
make disassembly for 911001 ROM as well.
make CPU clock pixelclock/2, and make separate 32MHz IO clock.
purge icache stuff out.
begin implementing simple CPU loop
add CPU reading function back in.
reinstate memory read value return function.
make IO run at 48MHz to enable timing closure.
make keyboard status asynchronous.
change baudrate divisors for serial monitor now that CPU clock is
96MHz.
plumb ioclock into the CPU, and adjust memory access waitstates
accordingly.
try to fix right border placement to prevent 2 pixel gap before
border.
drop IO speed and serial monitor speed to 32MHz.
serial monitor is now responsive.
bring memory write back into new CPU.  Calculate memory access
waitstates centrally with knowledge of clock phase relationships.
flatten keyboard matrix control logic to meet timing constraints.
begin replumbing monitor memory access interface so that we can
verify is memory access is working with refactored architecture.
fix plumbing for serial port monitor to allow memory reads and
writes.
don't clear memory access interfaces during wait states.
fix memory interface bugs.  serial monitor can now access fastram
and IO.