Pull in r214802 from upstream llvm trunk (by Renato Golin):

  Allow CP10/CP11 operations on ARMv5/v6

  Those registers are VFP/NEON and vector instructions should be used instead,
  but old cores rely on those co-processors to enable VFP unwinding. This change
  was prompted by the libc++abi's unwinding routine and is also present in many
  legacy low-level bare-metal code that we ought to compile/assemble.

  Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi.

This enables assembling certain ARM instructions used in libgcc.