Fix bit_word_funs::neq() for wide nodes

It appears that the implementation of this function was just plain
wrong.  I'm assuming nobody noticed it because there are
template-specialized versions of this template for narrow operations
(1, 2, and 3 words wide).  The specialized versions are implemented
correctly.

This really only matters for people who are VCD dumping signals that
are wider than 192 bits, as I don't think that any other code actually
uses this function.
Explicitly randomize initial Reg/Mem state in Verilog

VCS is broken and won't do this on its own.
Seed Verilog random numbers with RANDOM_SEED
Merge pull request #163 from palmer-dabbelt/long_equal

Fix bit_word_funs::neq() for wide nodes