Change how to get cacheline size

Some architecture does not support getting of LEVEL1_DCACHE_LINESIZE
by getconf. For example, ARM will return 0. Therefore, this can not be
built by architecture that is not supported LEVEL1_DCACHE_LINESIZE.
As far as I checked, 32bit architecture such as ARM, MIPS and other align
with 32.

This changes that set 32 to CACHELINE_SIZE when the LEVEL1_DCACHE_LINESIZE
returns 0.
It is difficult to cope in all architecture, but this can support much
architectures.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Clear x86-specific CPUFLAGS for maximum portability.
Merge pull request #30 from cybozu/fix-siphash

avoid breaking strict aliasing rule
add test of siphash