reset indices in FloBackend
fix emitRef
Necessary logic to AdvTester to stop isIdle from being too eager to say yes after posting last output
move findOrdering & findGraphDims from Module to Backend
use nodes instead of mods for code generation in VerilogBackend
reimplement findOrdering and use Driver.orderedNodes instead of omods for code generation in CppBackend
execuate addBindings only in the Verilog Backend
fix sortedComps and clean up
Merge branch 'master' of github.com:ucb-bar/chisel
remove preElaborateTransforms and clean up more
Merge branch 'master' into cpluspartition

Conflicts:
	src/main/scala/Backend.scala
	src/main/scala/Cpp.scala
	src/main/scala/Dot.scala
Remove unnecessary argument to PartitionIslands; Dot backend needs to explicitly call flatten() (to create Driver.orderedNodes).