msm: mdss: set vsync clock rate

Vsync clock rate is not set when vsync clock is enabled.
This cause command mode TE logic not works.

Change-Id: Ibf7dd07e53b2cd76ef30f13133368000c79ae149
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: acpuclock-krait: Program both high- and low-performance sources

The latest LDO/BHS switching sequence employed in the 8974
krait-regulator driver involves mandatory operations that cause
the CPUs to switch to the low-performance clock source when the
CPU is powered from the LDO, and to the high-performance clock
source when powered from the BHS.

This results in potential undervolting of the CPUs since the
acpuclock driver does not program the low-performance source,
and the clock source it selects be default is running at the
same speed as DDR (which can be very fast).

Fix this by programming both the high and low-performance clock
sources to be the same at all times.

CRs-Fixed: 538629
Change-Id: Iaa39cca9165b892e52acd8ec3aac5d0784112623
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>